From patchwork Fri Nov 17 18:21:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 119199 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp844874qgn; Fri, 17 Nov 2017 10:24:03 -0800 (PST) X-Google-Smtp-Source: AGs4zMbyCxdG2uGcokVDHXiN369d8tAwew8qGsUC2boIr++rC0EEnhscWCMRcx9LhbHtUGiUMOjS X-Received: by 10.101.101.215 with SMTP id y23mr1833166pgv.391.1510943043598; Fri, 17 Nov 2017 10:24:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510943043; cv=none; d=google.com; s=arc-20160816; b=qkcaNT4BYUHaMOXkrpk0Md+M9E7GRk33Z1eukKlXfaSh5GSNH1j4/eRJ0j/ymxe1b3 XidWf7cJrnmkdj1mLaj1vsuaE5/63pU+f/aER3nLPX7EWFiOQ+UeuN+mmpXEKZ+TQ8b6 m3y/nQAPnxqrgmcukjvwOLkN592G5rDo2PdSxO5rWJmME37Azte2JygUTVl3/YUkBpsa umPCocIIGhsxQUs/woL69Z/aGwoa2AEdgsd9Vd9Epbkrd6CsYSxN3nJUDN46bqUgyrAj N8WdAAIJjFkIBj0biEndXpvc79CKQuskvYdvD36NLaM+OvPAKBHEBBXAy5UYCGQ0yo5d z0JA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=GkCEVdH/uyVDhAUKbxsjwuvUXBGmovacScxMmjviJ2o=; b=MvAzhV4ZPyk3EiJ1Wi0suECvEPjc/IpyVQE9RsmRXp0eRwynLa+cV0NWkda7Fpf/FJ +Elpmxg1KtkcVlu49YrlSV60ubfMDxQSAagie+qj5fYMwvbBNQEc09pscnNBg4N0EsCS ZwHN6kKOhZSfYBX2B3dTZwJLlUKMCEyHE0eZNmC4vO3gbHxVWZw9kjScoa0zAkNtHq+P lWsbo2tBesr3jSjZ9p/EPM7HbzHDyw3UWnbpTNxyILxLOg8qKE4dbGA9X3YZ+N1fpEo+ E1radSsPKmLkwll0Fz0hY5QiAL5r+s7h8nE9oJYUcHzGZUbiEQhd+wjHAiH70NJg558w wcXg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l5si3219397pli.480.2017.11.17.10.24.03; Fri, 17 Nov 2017 10:24:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752535AbdKQSX7 (ORCPT + 28 others); Fri, 17 Nov 2017 13:23:59 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:39418 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760317AbdKQSWC (ORCPT ); Fri, 17 Nov 2017 13:22:02 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D903E1A9A; Fri, 17 Nov 2017 10:21:55 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AA5E23F246; Fri, 17 Nov 2017 10:21:55 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id DB1601AE10B5; Fri, 17 Nov 2017 18:22:03 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, Will Deacon Subject: [PATCH 16/18] arm64: entry: Add fake CPU feature for mapping the kernel at EL0 Date: Fri, 17 Nov 2017 18:21:59 +0000 Message-Id: <1510942921-12564-17-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1510942921-12564-1-git-send-email-will.deacon@arm.com> References: <1510942921-12564-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Allow explicit disabling of the entry trampoline on the kernel command line by adding a fake CPU feature (ARM64_MAP_KERNEL_AT_EL0) that can be used to apply alternative sequences to our entry code and avoid use of the trampoline altogether. Signed-off-by: Will Deacon --- arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/kernel/cpufeature.c | 11 +++++++++++ arch/arm64/kernel/entry.S | 6 +++++- arch/arm64/mm/mmu.c | 7 +++++++ 4 files changed, 25 insertions(+), 2 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 8da621627d7c..f61d85f76683 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -40,7 +40,8 @@ #define ARM64_WORKAROUND_858921 19 #define ARM64_WORKAROUND_CAVIUM_30115 20 #define ARM64_HAS_DCPOP 21 +#define ARM64_MAP_KERNEL_AT_EL0 22 -#define ARM64_NCAPS 22 +#define ARM64_NCAPS 23 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 21e2c95d24e7..aa6b90de6591 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -796,6 +796,12 @@ static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unus ID_AA64PFR0_FP_SHIFT) < 0; } +static bool map_kernel_at_el0(const struct arm64_cpu_capabilities *entry, + int __unused) +{ + return arm64_kernel_mapped_at_el0(); +} + static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", @@ -883,6 +889,11 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = hyp_offset_low, }, { + .capability = ARM64_MAP_KERNEL_AT_EL0, + .def_scope = SCOPE_SYSTEM, + .matches = map_kernel_at_el0, + }, + { /* FP/SIMD is not implemented */ .capability = ARM64_HAS_NO_FPSIMD, .def_scope = SCOPE_SYSTEM, diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index a600879939ce..a74253defc5b 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -73,6 +73,7 @@ .macro kernel_ventry, el, label, regsize = 64 .align 7 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +alternative_if_not ARM64_MAP_KERNEL_AT_EL0 .if \el == 0 .if \regsize == 64 mrs x30, tpidrro_el0 @@ -80,6 +81,7 @@ mov x30, xzr .endif .endif +alternative_else_nop_endif #endif sub sp, sp, #S_FRAME_SIZE @@ -300,6 +302,7 @@ alternative_if ARM64_WORKAROUND_845719 alternative_else_nop_endif #endif #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +alternative_if_not ARM64_MAP_KERNEL_AT_EL0 tramp_alias x30, tramp_exit_compat b 4f 3: @@ -308,6 +311,7 @@ alternative_else_nop_endif tramp_alias x30, tramp_exit_native 4: prfm plil1strm, [x30] +alternative_else_nop_endif #else 3: #endif @@ -332,7 +336,7 @@ alternative_else_nop_endif #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 .if \el == 0 - br x30 + alternative_insn "br x30", nop, ARM64_MAP_KERNEL_AT_EL0 .endif #endif eret diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 5ce5cb1249da..dab987f2912c 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -571,6 +571,13 @@ static int __init map_entry_trampoline(void) return 0; } core_initcall(map_entry_trampoline); + +static int __init parse_nokaiser(char *__unused) +{ + static_branch_disable(&__unmap_kernel_at_el0); + return 0; +} +__setup("nokaiser", parse_nokaiser); #else static void __init add_tramp_vma(void) {} #endif