From patchwork Fri Nov 17 18:21:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 119201 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp845268qgn; Fri, 17 Nov 2017 10:24:28 -0800 (PST) X-Google-Smtp-Source: AGs4zMaV2d4xW7Z6SNRFKUB1VL1Ha2NFMQiifYOXKcmt8bzma4RtARrr3D89i2OgwLklFYNYaftZ X-Received: by 10.101.85.9 with SMTP id f9mr5947509pgr.263.1510943068066; Fri, 17 Nov 2017 10:24:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510943068; cv=none; d=google.com; s=arc-20160816; b=KT90DAmJg3oG7tqKsjNQcvIKG9RQlQLjS0i4GnaGc1NGW0Y3YT9wrlqXxkCQOJf/ki auslLRpx7wsGo+jNv9GIVzaXFEtzmc1w7ZCfeodf55A5gscc3l2fCKCsOm0B19Iinq4/ +idh39oxw2035HDMiFi3UOMSPTkKZSNAun0qxe91ty/rxVeacoKaLhcLPQlXy5Qn5/6h JqUux29e8DpMJttEb+5Ob1Elg0aGijY4HS58HlDwpEgJi9b0YUJEWcx7LXPXh5JtW73B 5eMWeD9eGWu1jKXT1szvAhZMdYtkGl2kwgz8KTAUFxsofdAq1mdrjDN5/2qmGy28Zs3q lBnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=0ToogaDsbG1kH6QnLlZfj52hArCSoT6d86JumPJ2T0s=; b=VW/c4RaKS/nCFZNoCsj1uKFHEGzW0Tb9plPwfLjjRPlLrOQE1lHgbje0OGsYIZvt6y 4ySEY8fCZRMJVdc92fvuKsnawJy2B29fxkPSUGLgLb6cExnVx34NNSBKre6gVc/bIM6l 99UkY84NfOQotYF+ghaAdH+7Y33n7q0daH5RtLrpyCj/idPfPF3lK7Ir1P9dpy+1nfHW 2gBzEpHoJbk8b4bqYjBFKQb8x5PnpAnDjGf288H++hhV9Q4IYdyGoaA9xYoXQXXDly90 HlG09gQrdcnDxDBMWz2gD5BZbPSLXGL1zejnwbRpuAkI8bK3z7ZOrdtIZLHEJQG6L+LU HcMA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l5si3219397pli.480.2017.11.17.10.24.27; Fri, 17 Nov 2017 10:24:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760385AbdKQSYY (ORCPT + 28 others); Fri, 17 Nov 2017 13:24:24 -0500 Received: from foss.arm.com ([217.140.101.70]:39416 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760306AbdKQSV7 (ORCPT ); Fri, 17 Nov 2017 13:21:59 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6075F19E8; Fri, 17 Nov 2017 10:21:55 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 310FE3F7B0; Fri, 17 Nov 2017 10:21:55 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id CCC341AE13AC; Fri, 17 Nov 2017 18:22:03 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, Will Deacon Subject: [PATCH 15/18] arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks Date: Fri, 17 Nov 2017 18:21:58 +0000 Message-Id: <1510942921-12564-16-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1510942921-12564-1-git-send-email-will.deacon@arm.com> References: <1510942921-12564-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We zero tpidrro_el0 on return to the exception trampoline since it is used as a scratch register during exception entry. When the entry trampoline is being used, we can therefore avoid zeroing tpidrro_el0 in the context-switch for native tasks. Signed-off-by: Will Deacon --- arch/arm64/kernel/process.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) -- 2.1.4 diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 2dc0f8482210..c2841bda60be 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -305,16 +305,14 @@ void tls_preserve_current_state(void) static void tls_thread_switch(struct task_struct *next) { - unsigned long tpidr, tpidrro; - tls_preserve_current_state(); - tpidr = *task_user_tls(next); - tpidrro = is_compat_thread(task_thread_info(next)) ? - next->thread.tp_value : 0; + if (is_compat_thread(task_thread_info(next))) + write_sysreg(next->thread.tp_value, tpidrro_el0); + else if (arm64_kernel_mapped_at_el0()) + write_sysreg(0, tpidrro_el0); - write_sysreg(tpidr, tpidr_el0); - write_sysreg(tpidrro, tpidrro_el0); + write_sysreg(*task_user_tls(next), tpidr_el0); } /* Restore the UAO state depending on next's addr_limit */