From patchwork Fri Nov 17 18:21:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 119196 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp843946qgn; Fri, 17 Nov 2017 10:22:57 -0800 (PST) X-Google-Smtp-Source: AGs4zMbsYjn3KYAFaaKjzulAhH1/XJ4fOmIgvC/v/wqUCgYcL3lk9/6xiCF8hBoQamdC38H0m2w2 X-Received: by 10.99.97.66 with SMTP id v63mr5723900pgb.84.1510942977634; Fri, 17 Nov 2017 10:22:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510942977; cv=none; d=google.com; s=arc-20160816; b=Ezeae+YqxkMf9x8wsTdCBy/UQwte4s8P/IHs6uIqc2sdj9l1n+cHAdh4D55UHXz+yP i2uzEf66+J3aST6DxAgnTym4ayVOjxhTdGs2rN2BfLpMemqMsRRSlzRCZXoT2T1qxMND kfVHxjYazzq6n00AlTd9H9+DdNbLXFvaFGNEazMLLIKrd79fghed+jFGopf+/wpEIQgi JHKFXQs2FYQScWqZZWdq1S8rPD497Lcc5ktNRaQI8jJuWMGbmVRDadNbynem8VFG/Ioy 1TF2CgNhPR/mm4UbJVAH7TGfjH8kDqpC9eu7emfqM4E8cAtCTWfba9/JnTnSbO4le80P aLxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=dYak26K3sstZnUZAlKJH7mYKPDTAe3NjCY/sd9YQXjA=; b=id42YAz2AHh+r6tn6nSTMQl+ny56IdygzNQkl/DxJ2kNL22exeOoLjkYGpWfbxDn+p R92Qf4NVQsyMxnIpOdMJt4BwpLka6albwfxyjfHJJwGJ/d1ZAJY5dguDdmiQAfkiK1q8 ZgYkN1h5MIVIZRZrJB8vTqYCGJKqmxBEbry3fAoVjCeTE8ijdrHf2/7VtiHgK8y/FShN WZNcONvXQ0E4nMRJP8CKIQzo/VJCYybuLyVpHKLurADfeNtgGx+CyVZKEQu4XLMvfs9N oWhBfUixlxUmUqypuRBlXAbJc69zuzU5Ww4sInTsP2pKZKg9nG7nS0mda7y07bEF8mZZ KmDA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e11si3071081pgr.80.2017.11.17.10.22.57; Fri, 17 Nov 2017 10:22:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760281AbdKQSWx (ORCPT + 28 others); Fri, 17 Nov 2017 13:22:53 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:39472 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760302AbdKQSV7 (ORCPT ); Fri, 17 Nov 2017 13:21:59 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4412319CC; Fri, 17 Nov 2017 10:21:55 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 15F513F703; Fri, 17 Nov 2017 10:21:55 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id BE8081AE13AB; Fri, 17 Nov 2017 18:22:03 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, Will Deacon Subject: [PATCH 14/18] arm64: erratum: Work around Falkor erratum #E1003 in trampoline code Date: Fri, 17 Nov 2017 18:21:57 +0000 Message-Id: <1510942921-12564-15-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1510942921-12564-1-git-send-email-will.deacon@arm.com> References: <1510942921-12564-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We rely on an atomic swizzling of TTBR1 when transitioning from the entry trampoline to the kernel proper on an exception. We can't rely on this atomicity in the face of Falkor erratum #E1003, so on affected cores we can issue a TLB invalidation prior to jumping into the kernel. There is still the possibility of a TLB conflict here due to conflicting walk cache entries, but this doesn't appear to be the case on these CPUs in practice. Signed-off-by: Will Deacon --- arch/arm64/Kconfig | 17 +++++------------ arch/arm64/kernel/entry.S | 8 ++++++++ 2 files changed, 13 insertions(+), 12 deletions(-) -- 2.1.4 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0df64a6a56d4..f0fcbfc2262e 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -504,20 +504,13 @@ config CAVIUM_ERRATUM_30115 config QCOM_FALKOR_ERRATUM_1003 bool "Falkor E1003: Incorrect translation due to ASID change" default y - select ARM64_PAN if ARM64_SW_TTBR0_PAN help On Falkor v1, an incorrect ASID may be cached in the TLB when ASID - and BADDR are changed together in TTBRx_EL1. The workaround for this - issue is to use a reserved ASID in cpu_do_switch_mm() before - switching to the new ASID. Saying Y here selects ARM64_PAN if - ARM64_SW_TTBR0_PAN is selected. This is done because implementing and - maintaining the E1003 workaround in the software PAN emulation code - would be an unnecessary complication. The affected Falkor v1 CPU - implements ARMv8.1 hardware PAN support and using hardware PAN - support versus software PAN emulation is mutually exclusive at - runtime. - - If unsure, say Y. + and BADDR are changed together in TTBRx_EL1. Since we keep the ASID + in TTBR1_EL1, this situation only occurs in the entry trampoline and + then only for entries in the walk cache, since the leaf translation + is unchanged. Work around the erratum by invalidating the walk cache + entries for the trampoline before entering the kernel proper. config QCOM_FALKOR_ERRATUM_1009 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index a839b94bba05..a600879939ce 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -941,6 +941,14 @@ __ni_sys_trace: sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) bic \tmp, \tmp, #USER_ASID_FLAG msr ttbr1_el1, \tmp +alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 + isb + movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) + movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) + movk \tmp, #:abs_g0_nc:(TRAMP_VALIAS >> 12) + tlbi vae1, \tmp + dsb nsh +alternative_else_nop_endif .endm .macro tramp_unmap_kernel, tmp