From patchwork Fri Nov 17 18:21:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 119204 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp845772qgn; Fri, 17 Nov 2017 10:24:58 -0800 (PST) X-Google-Smtp-Source: AGs4zMZSKChmk8zjfmK9yKYvL4j+PT4dzDsJoku2+gsBbIkDqKcMHR34vjLNeSbQbRAya6E0INPz X-Received: by 10.159.218.66 with SMTP id x2mr4059656plv.326.1510943098820; Fri, 17 Nov 2017 10:24:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510943098; cv=none; d=google.com; s=arc-20160816; b=i0IBgbXJEPXFxmQUtGm3YYSyALExlj9hPkT1+9XRGZWukqVJOIKef8+6cxALOzhdF6 XBh6kaIWUEdTNBSLQKAshkG5ViIld5J2rjxHODRRd/48HzqQ6dfdGa5l6m6o2j1xfcoE TBDI6NhKteftdq0knFrtBEiYiSHp/P7VpHKfJHCVxDp++4r0aqD5RuYVRBxLyN20aIn8 hXn4B6Nw1sJrXkFlkhtyQR0WlTXd+u5aXBlz4Qlka9FcQh7pF3x4/MYWMfly0qpZGoBH aTaMmQAX4hY/60M4Xs+eq7q4rPtL3tFv5WRtSo4N/O0JUXWowQYjb5XqWBqmkbe1TGnC LsWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=+UUaiSbTiwSkmk2v0Bra6AufRm8d5j9mO1jvW6Vz9UU=; b=h4N0e3D5dzDhSDCBOR5fZLdpVYR+jK1hsU9d6X7hFTZGYMUWrDWsOT4M4EzhKesFNL bzcUspMnS/sf/w5BFaeT+1YsQHC7mLOtpsINonhPLBvKb1kaNpf1n2BJaz02DV2U9zeQ xTz7CMVyy6uhnTbcRwxtwUqmC5nrjsfzjWLZShsFVK1HoIoEAdTQaDy7C3/dUFEEgWR5 +5WXOLL0qMPbAgnFkegUPJEHGgDe5qCpzhgYjVxhsRdxECsHWo5vennk1jdWIr5xtHIJ Hpq23+OvFbhPKOuiZrN/Y6we1DzfzE9tFmHP6kHfhY6rPB+f+kS0WNubiolws1dXJdy8 dKiA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y62si3088438pgb.383.2017.11.17.10.24.58; Fri, 17 Nov 2017 10:24:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760478AbdKQSY5 (ORCPT + 28 others); Fri, 17 Nov 2017 13:24:57 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:39462 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760297AbdKQSV5 (ORCPT ); Fri, 17 Nov 2017 13:21:57 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3B11E199B; Fri, 17 Nov 2017 10:21:55 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0CFE63F5A0; Fri, 17 Nov 2017 10:21:55 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id AE3931AE1396; Fri, 17 Nov 2017 18:22:03 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, Will Deacon Subject: [PATCH 13/18] arm64: entry: Hook up entry trampoline to exception vectors Date: Fri, 17 Nov 2017 18:21:56 +0000 Message-Id: <1510942921-12564-14-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1510942921-12564-1-git-send-email-will.deacon@arm.com> References: <1510942921-12564-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hook up the entry trampoline to our exception vectors so that all exceptions from and returns to EL0 go via the trampoline, which swizzles the vector base register accordingly. Transitioning to and from the kernel clobbers x30, so we use tpidrro_el0 and far_el1 as scratch registers for native tasks. Signed-off-by: Will Deacon --- arch/arm64/kernel/entry.S | 46 ++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 6 deletions(-) -- 2.1.4 diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index e98cf3064509..a839b94bba05 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -72,6 +72,16 @@ .macro kernel_ventry, el, label, regsize = 64 .align 7 +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 + .if \el == 0 + .if \regsize == 64 + mrs x30, tpidrro_el0 + .else + mov x30, xzr + .endif + .endif +#endif + sub sp, sp, #S_FRAME_SIZE #ifdef CONFIG_VMAP_STACK /* @@ -118,6 +128,11 @@ b el\()\el\()_\label .endm + .macro tramp_alias, dst, sym + mov_q \dst, TRAMP_VALIAS + add \dst, \dst, #(\sym - .entry.tramp.text) + .endm + .macro kernel_entry, el, regsize = 64 .if \regsize == 32 mov w0, w0 // zero upper 32 bits of x0 @@ -265,25 +280,39 @@ alternative_else_nop_endif 2: #endif + msr elr_el1, x21 // set up the return data + msr spsr_el1, x22 + ldr lr, [sp, #S_LR] + .if \el == 0 ldr x23, [sp, #S_SP] // load return stack pointer msr sp_el0, x23 + tbz x22, #4, 3f + #ifdef CONFIG_ARM64_ERRATUM_845719 alternative_if ARM64_WORKAROUND_845719 - tbz x22, #4, 1f #ifdef CONFIG_PID_IN_CONTEXTIDR mrs x29, contextidr_el1 msr contextidr_el1, x29 #else msr contextidr_el1, xzr #endif -1: alternative_else_nop_endif #endif +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 + tramp_alias x30, tramp_exit_compat + b 4f +3: + msr tpidrro_el0, xzr + msr far_el1, x30 + tramp_alias x30, tramp_exit_native +4: + prfm plil1strm, [x30] +#else +3: +#endif .endif - msr elr_el1, x21 // set up the return data - msr spsr_el1, x22 ldp x0, x1, [sp, #16 * 0] ldp x2, x3, [sp, #16 * 1] ldp x4, x5, [sp, #16 * 2] @@ -299,9 +328,14 @@ alternative_else_nop_endif ldp x24, x25, [sp, #16 * 12] ldp x26, x27, [sp, #16 * 13] ldp x28, x29, [sp, #16 * 14] - ldr lr, [sp, #S_LR] add sp, sp, #S_FRAME_SIZE // restore sp - eret // return to kernel + +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 + .if \el == 0 + br x30 + .endif +#endif + eret .endm .macro irq_stack_entry