From patchwork Fri Nov 17 18:21:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 119205 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp846033qgn; Fri, 17 Nov 2017 10:25:12 -0800 (PST) X-Google-Smtp-Source: AGs4zMYak5j7JyYWd9IZ6TX1zDrpGQeT+QN2t71CpcBkQUMe38XydqVaZmXrYwrj4JGMQ9a1FyZ8 X-Received: by 10.101.73.8 with SMTP id p8mr6039339pgs.106.1510943112223; Fri, 17 Nov 2017 10:25:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510943112; cv=none; d=google.com; s=arc-20160816; b=j5F4MeCH0lXlUOwc5loA7W7qL1+1KvU1tZ1SLs92otxp/9xXX+aZ+Y90naiSrFmjm3 wtQs4CaGuFZzf7t6iCht1snXL0qsP0lW/M+044fqZhnsWGl5oef9bU7UozTuoBzRTeEH bkW21BKkzZEK2jP4L8pM/Ergn7AeHKzPI2AtMXlQM/fUlSPVQ3xGQdr60+iVaRZCrSpP b48vPSeh+e3iN4KuD+EPpB+ERRjjjMCzCFWu0rN0sJMlzDD18YLsYuuhx2QDwbxcxoYa FQjLzr8/7cUUHlSHbrXbEDKR3dpLxFzKa77/Gn5N4SvjZQLBMdfumMPqol4antrTThh6 pAPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=leKaMMVmuSX47rIR+EIgMDAFUVUxDkOfi9X26xuXjDc=; b=tbzOYDsf7wRAYuWZHEW3NhJ2xQdmDd1hlRCLNBgK/ev2wxOn4MCrBqTNJ1bJC4SzgV bikz2N+0I+K9qFxun+26CacXIp+4t2ptPbbIwGCCDiQOi53QbMR7VFt5h5zJwo26tpwc OFOT83Gxvvyg3BIWi2XDfg0qapw1OuVB6qZ+W7nHiJcaBd9WmVIrPqZYcsplBoVQ1+to +HUrzS+1OM8j+GbUPjXU3j9A8jzVqSzDTLc6VVWh1x34vORTVJRF8JChMTk3bdBqQqT5 jVDrrSFRvGaKyNld76fObQm0peiwYwb7qxr5lMw9rDKruDIkvYd6N6Gr3nci9/vhx6PQ /FPA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y62si3088438pgb.383.2017.11.17.10.25.11; Fri, 17 Nov 2017 10:25:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760507AbdKQSZJ (ORCPT + 28 others); Fri, 17 Nov 2017 13:25:09 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:39458 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760294AbdKQSV4 (ORCPT ); Fri, 17 Nov 2017 13:21:56 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 175F016BA; Fri, 17 Nov 2017 10:21:55 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DDBC63F7B0; Fri, 17 Nov 2017 10:21:54 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 6D12A1AE1373; Fri, 17 Nov 2017 18:22:03 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, Will Deacon Subject: [PATCH 09/18] arm64: mm: Invalidate both kernel and user ASIDs when performing TLBI Date: Fri, 17 Nov 2017 18:21:52 +0000 Message-Id: <1510942921-12564-10-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1510942921-12564-1-git-send-email-will.deacon@arm.com> References: <1510942921-12564-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since an mm has both a kernel and a user ASID, we need to ensure that broadcast TLB maintenance targets both address spaces so that things like CoW continue to work with the uaccess primitives in the kernel. Signed-off-by: Will Deacon --- arch/arm64/include/asm/tlbflush.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index af1c76981911..42d250ec74b1 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -23,6 +23,7 @@ #include #include +#include /* * Raw TLBI operations. @@ -54,6 +55,11 @@ #define __tlbi(op, ...) __TLBI_N(op, ##__VA_ARGS__, 1, 0) +#define __tlbi_user(op, arg) do { \ + if (!arm64_kernel_mapped_at_el0()) \ + __tlbi(op, (arg) | USER_ASID_FLAG); \ +} while (0) + /* * TLB Management * ============== @@ -115,6 +121,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm) dsb(ishst); __tlbi(aside1is, asid); + __tlbi_user(aside1is, asid); dsb(ish); } @@ -125,6 +132,7 @@ static inline void flush_tlb_page(struct vm_area_struct *vma, dsb(ishst); __tlbi(vale1is, addr); + __tlbi_user(vale1is, addr); dsb(ish); } @@ -151,10 +159,13 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, dsb(ishst); for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) { - if (last_level) + if (last_level) { __tlbi(vale1is, addr); - else + __tlbi_user(vale1is, addr); + } else { __tlbi(vae1is, addr); + __tlbi_user(vae1is, addr); + } } dsb(ish); } @@ -194,6 +205,7 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, unsigned long addr = uaddr >> 12 | (ASID(mm) << 48); __tlbi(vae1is, addr); + __tlbi_user(vae1is, addr); dsb(ish); }