From patchwork Sun Oct 29 21:20:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 117419 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1853673qgn; Sun, 29 Oct 2017 14:24:31 -0700 (PDT) X-Google-Smtp-Source: ABhQp+R5I75bwwtMXMnQk/JeYGV+9R8gitP3bUZ5u+SJ+mN6rHAnsK4nUWrUS5mYGUUWoGT4lg0F X-Received: by 10.98.204.157 with SMTP id j29mr6805784pfk.236.1509312271064; Sun, 29 Oct 2017 14:24:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509312271; cv=none; d=google.com; s=arc-20160816; b=SpJB963vt+qtokAu4vx2H4KnqFSeeIM1ax6K5zxUDIxjIF/ZVkPepJrsPn3nQGF9IT 129SZdmyekK1bl9tSwgmaWVJxvmn0uRMGR42+f0BvHYt5ZHcntJBzqZR02i6fBJm9/Ga 5b/+UapO4Atn1I8611zEvRaoRCJOPddj4fQrGyh1sUiZLKy2WV5gkoqBLDIIkgIgtf1H 0aTqdkkDMVVOh5IuODjLrgqFVIxifC5WwKsQuMppSqkIyCbIAwY0tIb8S7RwXQ5e18xP dfi16FjvaGkLgZVGpeaT8fIjmglugjgmDUP7eQf/TY2itwr0wyJkqWppFmUjwzg/Vxct OHKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=zvQvEzF4U1EyertfYmCwOgpa2MT7RxXPj5d2gBeT/ig=; b=hNFLIdHs+wfb8zKYmInQ6j7KNN6B7BEjCOSoye2b/Al2p1jOZskzN11AjQOEGtohV4 VY7tnmpsKRtsI19xu8LXiLWN2w2pt+OaTNqEiCNKK02dlknRJW+blB75SXsAn3XsWufu TRUpo8FKo+PVGdknvzbEdTPuF9KT5tLgN8Fujro7+adThmM5Sy2SlkYkTLOsd0VC4Swi 1a8z9wBNd1bPwCYOjTpss8toX1XbWFNIx7XWdW/klTKxfpBLwyLWyNAQtcmI94N1ZiE8 6EMFqd5tlSaeiKWU+NrQOAjG4ITirUxzaFnfFDpYd4tfUj4wMf/M5U6jdiEu5hUVlhaK zAsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fCYwW5r/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 62si8504826pgh.81.2017.10.29.14.24.30; Sun, 29 Oct 2017 14:24:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fCYwW5r/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932208AbdJ2VY2 (ORCPT + 27 others); Sun, 29 Oct 2017 17:24:28 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:47757 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752100AbdJ2VY0 (ORCPT ); Sun, 29 Oct 2017 17:24:26 -0400 Received: by mail-wm0-f65.google.com with SMTP id r196so12189150wmf.2 for ; Sun, 29 Oct 2017 14:24:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zvQvEzF4U1EyertfYmCwOgpa2MT7RxXPj5d2gBeT/ig=; b=fCYwW5r/UZ9Rp9TJ8AX2o3GCFfT3hWYF9URIjwRaocDUNxU1igQsQNHeZ+nfjNZ6zq 1f4NJSYf5lsmfAFdOWLK2gX9ciOYBsI1LRX2hmNJBR9aZ9Ci9u1CmYLgsFWF73ZZ/FUf pTvmCrp57i14dRzLPNCMhz0zlBosh07uJuAsQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zvQvEzF4U1EyertfYmCwOgpa2MT7RxXPj5d2gBeT/ig=; b=jWO15Qq73vqPAd0rOh8sfiXfVEkHlGxWx88NcRS8YC8dbt7PPjDZ4nW4CEXkioQhMY fNANh6FOJ0bBEBGXxrqTJxRZou1WAnnHHUlWPGCwQsNQVpx97MeV3ld7u2FNRFJ0eIwe Tmk7S2tYjmDBM+fzKupU96ifU4dV3UoYgSC3X9l6FfSjWc/T6eP89OSv5Vr6s44ljY5A Ksqf7/Lhr1pDOHZ8wb/uHqJpDkrYp9PjRR16IDhlWiqW7+BjQ1o50wp+94jyWBejiuHi elEyQJ22/GOvJKAepW5sZ5FmNpUXi2sIs1SenhV527O/A9rNu8uZBuTlCxXR38DLnBQt kGOA== X-Gm-Message-State: AMCzsaXVjIiCjOrnIFEegCtT1xFy979mt/7uUupHlp5Q8uuAxjl9I7nI DIjOrSiHhp3C/RwLtAPrSetQLw== X-Received: by 10.28.229.149 with SMTP id c143mr1841864wmh.156.1509312264872; Sun, 29 Oct 2017 14:24:24 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:24 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 04/17] clocksource/drivers/sh_cmt: Remove support for "renesas, cmt-32*" Date: Sun, 29 Oct 2017 22:20:21 +0100 Message-Id: <1509312035-17368-4-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Geert Uytterhoeven Remove driver matching support for the unused "renesas,cmt-32" and "renesas,cmt-32-fast" compatible values, cfr. commit 203bb3479958c48a ("devicetree: bindings: Remove unused 32-bit CMT bindings"). As this removes the last user of SH_CMT_32BIT_FAST, all support for this variant is removed from the driver. Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Daniel Lezcano --- drivers/clocksource/sh_cmt.c | 20 -------------------- 1 file changed, 20 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 45af436..8546736 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -66,7 +66,6 @@ struct sh_cmt_device; enum sh_cmt_model { SH_CMT_16BIT, SH_CMT_32BIT, - SH_CMT_32BIT_FAST, SH_CMT_48BIT, SH_CMT0_RCAR_GEN2, SH_CMT1_RCAR_GEN2, @@ -203,16 +202,6 @@ static const struct sh_cmt_info sh_cmt_info[] = { .read_count = sh_cmt_read32, .write_count = sh_cmt_write32, }, - [SH_CMT_32BIT_FAST] = { - .model = SH_CMT_32BIT_FAST, - .width = 32, - .overflow_bit = SH_CMT32_CMCSR_CMF, - .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), - .read_control = sh_cmt_read16, - .write_control = sh_cmt_write16, - .read_count = sh_cmt_read32, - .write_count = sh_cmt_write32, - }, [SH_CMT_48BIT] = { .model = SH_CMT_48BIT, .channels_mask = 0x3f, @@ -890,13 +879,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, case SH_CMT_48BIT: ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; break; - case SH_CMT_32BIT_FAST: - /* - * The 32-bit "fast" timer has a single channel at hwidx 5 but - * is located at offset 0x40 instead of 0x60 for some reason. - */ - ch->ioctrl = cmt->mapbase + 0x40; - break; case SH_CMT0_RCAR_GEN2: case SH_CMT1_RCAR_GEN2: ch->iostart = cmt->mapbase + ch->hwidx * 0x100; @@ -952,8 +934,6 @@ static const struct platform_device_id sh_cmt_id_table[] = { MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { - { .compatible = "renesas,cmt-32", .data = &sh_cmt_info[SH_CMT_32BIT] }, - { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] }, { .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },