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[209.132.180.67]) by mx.google.com with ESMTP id k76si8583155pgc.537.2017.10.29.14.27.52; Sun, 29 Oct 2017 14:27:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AQrM7sBk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751273AbdJ2V1u (ORCPT + 27 others); Sun, 29 Oct 2017 17:27:50 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:51117 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751875AbdJ2VYX (ORCPT ); Sun, 29 Oct 2017 17:24:23 -0400 Received: by mail-wr0-f196.google.com with SMTP id p96so10679657wrb.7 for ; Sun, 29 Oct 2017 14:24:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=byssf5KV/rW+pY6zRYLULSOrhaD+/7yyQbZWHqg2eU4=; b=AQrM7sBkPi9F+X7Y1B6opoD0pfx9irELhm3fWIx+DiqsDV5W40w6HEmSAMx1gCTHy1 Yc8J+m9pj8hfRLByXDs511i1XiAURmz3gXYZHKwqri74sOgRZ+tmyWJGY4fBgO0lDdZe 8ili9gaSx4h0vQ/8qF0hDwo6j8al1QfBqhGQU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=byssf5KV/rW+pY6zRYLULSOrhaD+/7yyQbZWHqg2eU4=; b=BRT1PZA8c/YC1j6GRkExjYnxSeVhIHyGy8N2QqNGD4Rb9WnQXf+9SrA+XRsd/U5KRb N6fIPOGte4u3W6hvm0vm7SoSN1BXZl6uXr1ygiCzPB2T0ZI1aJGGuoc0zJhjWbGmGd0Q GvwyV3dALOTyxk7BtrjurZWzHenrd8zR2GmX4+Pv6F8f71UM9W5wOWwbtehiHwYXTRR5 cPJvuTYVn3w0qmec2Q6sHN4cYjT7xBDdA9RUuUiTG1K7ttwVdJ9CwZ+uhVY99ddvb438 hKFP0rTVsVJqe445+Clg/rlxebDDYKogHv/dK0gOT564sdFN3lhwzb8d0xT5LK8SwUA/ +nrw== X-Gm-Message-State: AMCzsaULJD81CTUslWKxoWg3E5oXRRcmlNVZeOpnO3fC9vegpOAKBMT4 dNYhjLYZo7zyKfMQJcv5PfTJ+A== X-Received: by 10.223.184.125 with SMTP id u58mr5552072wrf.8.1509312261860; Sun, 29 Oct 2017 14:24:21 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c92:b7e6:9f71:ab86]) by smtp.gmail.com with ESMTPSA id z20sm10067264wrz.62.2017.10.29.14.24.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Oct 2017 14:24:21 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, Magnus Damm , Geert Uytterhoeven , Laurent Pinchart Subject: [PATCH 02/17] clocksource/drivers/sh_cmt: Use 0x3f mask for SH_CMT_48BIT case Date: Sun, 29 Oct 2017 22:20:19 +0100 Message-Id: <1509312035-17368-2-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> References: <1509312035-17368-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Magnus Damm Always use 0x3f as channel mask for the SH_CMT_48BIT type of devices. Once this patch is applied the "renesas,channels-mask" property will be ignored by the driver for older devices matching SH_CMT_48BIT. In the future when all CMT types store channel mask in the driver then we will be able to deprecate and remove "renesas,channels-mask" from DTS. Signed-off-by: Magnus Damm Acked-by: Laurent Pinchart Reviewed-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven Signed-off-by: Daniel Lezcano --- drivers/clocksource/sh_cmt.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index e09e8bf..c104c80 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -74,6 +74,8 @@ enum sh_cmt_model { struct sh_cmt_info { enum sh_cmt_model model; + unsigned int channels_mask; + unsigned long width; /* 16 or 32 bit version of hardware block */ unsigned long overflow_bit; unsigned long clear_bits; @@ -212,6 +214,7 @@ static const struct sh_cmt_info sh_cmt_info[] = { }, [SH_CMT_48BIT] = { .model = SH_CMT_48BIT, + .channels_mask = 0x3f, .width = 32, .overflow_bit = SH_CMT32_CMCSR_CMF, .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), @@ -966,9 +969,14 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) id = of_match_node(sh_cmt_of_table, pdev->dev.of_node); cmt->info = id->data; - ret = sh_cmt_parse_dt(cmt); - if (ret < 0) - return ret; + /* prefer in-driver channel configuration over DT */ + if (cmt->info->channels_mask) { + cmt->hw_channels = cmt->info->channels_mask; + } else { + ret = sh_cmt_parse_dt(cmt); + if (ret < 0) + return ret; + } } else if (pdev->dev.platform_data) { struct sh_timer_config *cfg = pdev->dev.platform_data; const struct platform_device_id *id = pdev->id_entry;