From patchwork Thu Oct 12 12:30:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 115621 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp1885171qgn; Thu, 12 Oct 2017 05:31:56 -0700 (PDT) X-Google-Smtp-Source: AOwi7QANQm0mJMqPvG231MnGgsWSA5gGuCDpCTtuBqMU8n+qhSoQ4YBAR5PKamGiXnzJqQhvlkbe X-Received: by 10.99.109.75 with SMTP id i72mr120646pgc.268.1507811516454; Thu, 12 Oct 2017 05:31:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507811516; cv=none; d=google.com; s=arc-20160816; b=Mbt/seTdT3PpPo/mjYd9n17XtyC9PQ/C7XxsiAoGBdJ17kpoNSZMw+VDxenkM6MKJ7 T14e1LmzONjrK2RghnxwbqeIYChC60df5vw3oOHBEaGMRkTJwVLi1YJoypgVwFyDhgO2 bDL4bgIn4v+CXweuuY5KvmJv45eLpvhebbETzP2WBms3DWEJASsrZGI5d47ONKqgNAW/ IBH5d/2467ESSLwwuCTaIZK+7CPTbor8/q02ucA/XvXwhxouTkDz2QSNm17gnj05MSkg fSMmfASHJVn/firq8V9Ss+OPuV6TUOGkj+hgByvCHU/b/XDL3x4b+jnI3ybqZexja/Eh iIiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=lHD52JfVg6o3L4Ly6/kO+7SdSpwS8l4dGQjDogMTCoA=; b=IDkb4B7jC5rzdkjCiVEca13hsgMI2oWhww11wcm/jqWfenqGVfH/ebfrOfJWszKDBQ 4qPvr9C74snVojSVAAFrxa/BQcMNlsJ2pCL1EPTjRWaFpHm+h7YxSwR+TwPtMCu6bUgh tHugTUKH5555pobOKSiLFwzGuGNBtVNbSfqCw7n5JnTDfN72e/2tC84GmVrxw6WFZOVp bybEwenhxaDU00CWrk0EdH5p499M7OYwhNFyiPht8rFax/i0+BJyyoNzgUWN6D4DKmwk sVqOiDWIrs2oBbTY/nObfeXWhnPrF+43JZs5xkV+JQmYlp3Zlt3/XizAeJOh6JeOEtLP lNcQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q10si7935333pll.319.2017.10.12.05.31.56; Thu, 12 Oct 2017 05:31:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757590AbdJLMbz (ORCPT + 27 others); Thu, 12 Oct 2017 08:31:55 -0400 Received: from foss.arm.com ([217.140.101.70]:45890 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751004AbdJLMai (ORCPT ); Thu, 12 Oct 2017 08:30:38 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CA967165C; Thu, 12 Oct 2017 05:30:37 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9C9DB3F599; Thu, 12 Oct 2017 05:30:37 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id AECFD1AE2F6D; Thu, 12 Oct 2017 13:30:40 +0100 (BST) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: marc.zyngier@arm.com, mark.rutland@arm.com, kim.phillips@arm.com, tglx@linutronix.de, peterz@infradead.org, alexander.shishkin@linux.intel.com, robh@kernel.org, suzuki.poulose@arm.com, pawel.moll@arm.com, mathieu.poirier@linaro.org, mingo@redhat.com, linux-kernel@vger.kernel.org, Will Deacon Subject: [PATCH v6 5/7] arm64: head: Init PMSCR_EL2.{PA, PCT} when entered at EL2 without VHE Date: Thu, 12 Oct 2017 13:30:36 +0100 Message-Id: <1507811438-2267-6-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1507811438-2267-1-git-send-email-will.deacon@arm.com> References: <1507811438-2267-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When booting at EL2, ensure that we permit the EL1 host to sample physical addresses and physical counter values using SPE. Acked-by: Mark Rutland Signed-off-by: Will Deacon --- arch/arm64/kernel/head.S | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) -- 2.1.4 diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 0b243ecaf7ac..cfa90a43fbe7 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -480,14 +480,21 @@ set_hcr: /* Statistical profiling */ ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer - cbz x0, 6f // Skip if SPE not present - cbnz x2, 5f // VHE? + cbz x0, 7f // Skip if SPE not present + cbnz x2, 6f // VHE? + mrs_s x4, SYS_PMBIDR_EL1 // If SPE available at EL2, + and x4, x4, #(1 << SYS_PMBIDR_EL1_P_SHIFT) + cbnz x4, 5f // then permit sampling of physical + mov x4, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \ + 1 << SYS_PMSCR_EL2_PA_SHIFT) + msr_s SYS_PMSCR_EL2, x4 // addresses and physical counter +5: mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) orr x3, x3, x1 // If we don't have VHE, then - b 6f // use EL1&0 translation. -5: // For VHE, use EL2 translation + b 7f // use EL1&0 translation. +6: // For VHE, use EL2 translation orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1 -6: +7: msr mdcr_el2, x3 // Configure debug traps /* Stage-2 translation */