From patchwork Fri Sep 22 03:46:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 113956 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2798931qgf; Thu, 21 Sep 2017 20:50:33 -0700 (PDT) X-Google-Smtp-Source: AOwi7QD//AnVYAFgM6e1s/pDj+zMmVptOGO9Bj2ufxm+i8FGr1ghfAOPNp5Ix+3FRCJfzHPLm+L6 X-Received: by 10.99.51.15 with SMTP id z15mr7766300pgz.287.1506052233367; Thu, 21 Sep 2017 20:50:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506052233; cv=none; d=google.com; s=arc-20160816; b=Yadre3Uwdz4Jb14NAaN5GwQurLy5mSNz3OdRCyGsj+Zvxz1tjQFdhw7/qPAh/zpy6X i/FdUlIRwhE7HbPTYed8lQ5y5TkXl/j+vRt7LsfbcgDSigGIexXcEskPJDJJNvWD1C4k pmtsgRB61G12SUEPghmpzkDX+dl0/ud2o7W2NvuMGtLEw9OADkNX+CuEF1lEXftasvfF 2B3i6yVVc2qyqmvB0CCKyLWcMGEKE137UJRKSDdVOKS/vlPYVXreA2sshzZL4ou80qGn ujQGKmnnlctRjc2q0lZ+R3vyv0avGsGEb3xYl6YZoAj1G3A0JuIqZ1dfoVTVILuuZ73Q DpWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=kKwi5RZmABL8IX6i/h0RYZXHIeP+oiLXX9aIpj7Ojb8=; b=tI+HOrw2XzaQag/8yqydc7CFRIlFbJvjIx2QMCKcJE3uAIj6u5sLWZn7ps4lpbx6gv XPe3g5sPz8e4wPT2yqL0hdVG77/YOQCIqQsEh0sqkwVQmKvsFoy8MlVsUSN1fXqnWkEY hrpYvHxRBSDSTPQRHhmPBphpE/+y+abcmcZmaxqHBGsYOfH/Sa77szd7coBX55A6ziuo KP5hq+oZE0KkYr5EX3bwcUYmfxhVS55D6M2ngyaRWWMYdDf1kNObrvMf9qcK5lRK47MT eTpHa28jpWGQRXe9WiYMP5CYOchqVoL4QlDlET6LSgMP5XcsCjwCGZlU0K92YUsIYuZH g5hQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=oPsR3+mB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x137si2058493pfd.259.2017.09.21.20.50.33; Thu, 21 Sep 2017 20:50:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=oPsR3+mB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752038AbdIVDub (ORCPT + 26 others); Thu, 21 Sep 2017 23:50:31 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:59411 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751726AbdIVDst (ORCPT ); Thu, 21 Sep 2017 23:48:49 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v8M3kwAQ029389; Fri, 22 Sep 2017 12:47:05 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8M3kwAQ029389 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1506052025; bh=kKwi5RZmABL8IX6i/h0RYZXHIeP+oiLXX9aIpj7Ojb8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oPsR3+mBHTX2IZNNaNkgVQSbDBKbWWKw39k5ixZyqQi+jHboxwwQ6yHTKDTlGaqfB KoOuNOvACjUOFzXmcvSEoKpna8GyqIwlZhFlWe6kfqHNfQ083L+g/BgCoouKG4eXx7 oHGCazet1VF9rp2dQJ28l9I76tExb1loPgjY67BUuZ1unZMpgEH8F5+LG33nMTrOjh KZTMfQWQ+Wkg/Dw4EhIJMBSr4HZmIhJeto7ovVPGnIpJcpbSrt4ks0oQljxif9byWt WaIuCPf74BWoHU5s7ki+/Cof7Sl5V0SWWT+L5L63CqhkbNX0Cp6xzgeYU38FQMF2Uj tlqowqleLqzzA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse Subject: [PATCH v2 07/12] mtd: nand: denali: use more FIELD_PREP / FIELD_GET where appropriate Date: Fri, 22 Sep 2017 12:46:44 +0900 Message-Id: <1506052009-8285-8-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> References: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In several places in this driver, the register fields are retrieved as follows: val = reg & FOO_MASK; Then, modified as follows: reg &= ~FOO_MASK; reg |= val; This code relies on its shift is 0, which we will never know until we check the definition of FOO_MASK. Use FIELD_PREP / FIELD_GET where appropriate. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mtd/nand/denali.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 1525c4e..ca98015 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -88,7 +88,7 @@ static void denali_detect_max_banks(struct denali_nand_info *denali) { uint32_t features = ioread32(denali->reg + FEATURES); - denali->max_banks = 1 << (features & FEATURES__N_BANKS); + denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features); /* the encoding changed from rev 5.0 to 5.1 */ if (denali->revision < 0x0501) @@ -374,7 +374,7 @@ static int denali_hw_ecc_fixup(struct mtd_info *mtd, return 0; } - max_bitflips = ecc_cor & ECC_COR_INFO__MAX_ERRORS; + max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor); /* * The register holds the maximum of per-sector corrected bitflips. @@ -985,7 +985,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + ACC_CLKS); tmp &= ~ACC_CLKS__VALUE; - tmp |= acc_clks; + tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks); iowrite32(tmp, denali->reg + ACC_CLKS); /* tRWH -> RE_2_WE */ @@ -994,7 +994,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + RE_2_WE); tmp &= ~RE_2_WE__VALUE; - tmp |= re_2_we; + tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we); iowrite32(tmp, denali->reg + RE_2_WE); /* tRHZ -> RE_2_RE */ @@ -1003,7 +1003,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + RE_2_RE); tmp &= ~RE_2_RE__VALUE; - tmp |= re_2_re; + tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re); iowrite32(tmp, denali->reg + RE_2_RE); /* tWHR -> WE_2_RE */ @@ -1012,7 +1012,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE; - tmp |= we_2_re; + tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re); iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE); /* tADL -> ADDR_2_DATA */ @@ -1026,8 +1026,8 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); - tmp &= ~addr_2_data_mask; - tmp |= addr_2_data; + tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA; + tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data); iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA); /* tREH, tWH -> RDWR_EN_HI_CNT */ @@ -1037,7 +1037,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); tmp &= ~RDWR_EN_HI_CNT__VALUE; - tmp |= rdwr_en_hi; + tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi); iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); /* tRP, tWP -> RDWR_EN_LO_CNT */ @@ -1051,7 +1051,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); tmp &= ~RDWR_EN_LO_CNT__VALUE; - tmp |= rdwr_en_lo; + tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo); iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); /* tCS, tCEA -> CS_SETUP_CNT */ @@ -1062,7 +1062,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + CS_SETUP_CNT); tmp &= ~CS_SETUP_CNT__VALUE; - tmp |= cs_setup; + tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup); iowrite32(tmp, denali->reg + CS_SETUP_CNT); return 0;