From patchwork Wed Sep 13 05:20:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 112407 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp536561qgf; Tue, 12 Sep 2017 22:24:43 -0700 (PDT) X-Google-Smtp-Source: ADKCNb5C42A6kY4sPuzdH/AybLRuhCn/s+XeWV0ZBfRYF1RRlJfOnKr13DK44SMpSAv0fNg18xGq X-Received: by 10.99.54.7 with SMTP id d7mr17086304pga.115.1505280283395; Tue, 12 Sep 2017 22:24:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505280283; cv=none; d=google.com; s=arc-20160816; b=xNr3hYBsbT0ISJHTT+HJNYZrQkbXFisU0YYaZMUszrl7tJomfWKporr9rBu0XDVRvW +idk8WxSY4EpTuk9a8Tps7BxVwR00DXuLci5lFD7d5YJ1gla8mX0VZWYhWcI1gEkGv0H swL8Z/YOavDh0uHLmJGffO7zfX5r6b2mMazdF6BdJNrRWYufz/8lF0L2Dagfjq/0kFIK Gvtw19H8DTkaJzidU+3rnyHv/WMdPetcc3E+0xBN+qcQbPASRIO6JokbMnewY8rUja0d b1LuVkmzq62GfhJV1Cfc2+xFmnqrQgzxKNPIdT0PUGz6vmdhmnL+QzHrRMt2J1bNwqcS eNlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=rPYi00FdhFvB5jlz8bzB2Hvp8WgSMWRgU9fFEH4ZVXE=; b=bjR6miGxglvahDT6rpkIm5/ALbklR002d7i2t0WHzxVRaP0ppNDr2r2D9dIk9Aayvv mAG+VBgVL2S/nMi/YhKwqmMcKtkFLxmH8LTbsbPE6rBJGjG8+Xc3YrreOuMWvYk9Rsjf c18oFqSCzKYZBlcrvUwzFTrGFKoGiNg2wPzcPuBldsIC1LbZ1xvQyIc5FpwF33S5LiNI eQtQyS5m2s1NTzC+jaUtDYbnuW+4hDkloTjYbfLy015e6i/YjS7MtHOTPWRY+VApLDQc WOUk9u2cG1unOtIZPC/AxAbQffPHvm29lmj4b7m4CZVKqHGOQjMLc5z2cAw+WkonRucx xSZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=mB0Gc+Db; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a77si9078872pfg.419.2017.09.12.22.24.43; Tue, 12 Sep 2017 22:24:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=mB0Gc+Db; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751953AbdIMFYl (ORCPT + 26 others); Wed, 13 Sep 2017 01:24:41 -0400 Received: from conuserg-12.nifty.com ([210.131.2.79]:35991 "EHLO conuserg-12.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751326AbdIMFW6 (ORCPT ); Wed, 13 Sep 2017 01:22:58 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-12.nifty.com with ESMTP id v8D5Kpx5010397; Wed, 13 Sep 2017 14:20:56 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com v8D5Kpx5010397 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1505280057; bh=rPYi00FdhFvB5jlz8bzB2Hvp8WgSMWRgU9fFEH4ZVXE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mB0Gc+Db66kuo8WJM0ZtwJ0DC/0QZyF5FiEEggJxrFoVCbBuN31oC1ydHEs9qdvbB +nCAwDY1x1vFq/zVJCn7BGEbALuj2PdrJsT29jtOhbnyAO1kTYMWtsh1POk2EDUVRe si8tF9W6GdWlPUKyHPBpbJFcoSjqZ6Ws2XzN4LynaxR1BkPpSWypvdYtzSqizp6d2W L+r9CE9uQpLwxv3gdpV9eqTBqV1mgfzq1IEVlFBai8nRS+1D1ZlTSYEr8iADoYnSky Z7T7zEB35BI+BN1f90/hy0ShTVN86NEX/rj9LAw7NyCSN8r1yeab9+ffhz81ywRWD/ gGN6rM1EGEExA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse Subject: [PATCH 6/9] mtd: nand: denali: clean up macros with Date: Wed, 13 Sep 2017 14:20:43 +0900 Message-Id: <1505280046-16608-7-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505280046-16608-1-git-send-email-yamada.masahiro@socionext.com> References: <1505280046-16608-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org All the register offsets and bitfield masks are defined in denali.h, but the driver code ended up with additional crappy macros such as MAKE_ECC_CORRECTION(), ECC_SECTOR(), etc. The reason is apparent - accessing a register field requires mask and shift pair. The denali.h only provides mask. However, defining both is tedious. provides a convenient way to get register fields only with a single shifted mask. Now use it. While I am here, I shortened some macros. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/denali.c | 25 +++++++++++-------------- drivers/mtd/nand/denali.h | 13 +++++-------- 2 files changed, 16 insertions(+), 22 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 3cc56de..1525c4e 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -17,6 +17,7 @@ * */ +#include #include #include #include @@ -386,13 +387,6 @@ static int denali_hw_ecc_fixup(struct mtd_info *mtd, return max_bitflips; } -#define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) -#define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) -#define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) -#define ECC_ERROR_UNCORRECTABLE(x) ((x) & ERR_CORRECTION_INFO__ERROR_TYPE) -#define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) -#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) - static int denali_sw_ecc_fixup(struct mtd_info *mtd, struct denali_nand_info *denali, unsigned long *uncor_ecc_flags, uint8_t *buf) @@ -410,18 +404,20 @@ static int denali_sw_ecc_fixup(struct mtd_info *mtd, do { err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS); - err_sector = ECC_SECTOR(err_addr); - err_byte = ECC_BYTE(err_addr); + err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr); + err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr); err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO); - err_cor_value = ECC_CORRECTION_VALUE(err_cor_info); - err_device = ECC_ERR_DEVICE(err_cor_info); + err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE, + err_cor_info); + err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE, + err_cor_info); /* reset the bitflip counter when crossing ECC sector */ if (err_sector != prev_sector) bitflips = 0; - if (ECC_ERROR_UNCORRECTABLE(err_cor_info)) { + if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) { /* * Check later if this is a real ECC error, or * an erased sector. @@ -451,7 +447,7 @@ static int denali_sw_ecc_fixup(struct mtd_info *mtd, } prev_sector = err_sector; - } while (!ECC_LAST_ERR(err_cor_info)); + } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR)); /* * Once handle all ecc errors, controller will trigger a @@ -1351,7 +1347,8 @@ int denali_init(struct denali_nand_info *denali) "chosen ECC settings: step=%d, strength=%d, bytes=%d\n", chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); - iowrite32(MAKE_ECC_CORRECTION(chip->ecc.strength, 1), + iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) | + FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength), denali->reg + ECC_CORRECTION); iowrite32(mtd->erasesize / mtd->writesize, denali->reg + PAGES_PER_BLOCK); diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index dc3f970..73aad3a 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -114,9 +114,6 @@ #define ECC_CORRECTION 0x1b0 #define ECC_CORRECTION__VALUE GENMASK(4, 0) #define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16) -#define MAKE_ECC_CORRECTION(val, thresh) \ - (((val) & (ECC_CORRECTION__VALUE)) | \ - (((thresh) << 16) & (ECC_CORRECTION__ERASE_THRESHOLD))) #define READ_MODE 0x1c0 #define READ_MODE__VALUE GENMASK(3, 0) @@ -258,13 +255,13 @@ #define ECC_ERROR_ADDRESS 0x630 #define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0) -#define ECC_ERROR_ADDRESS__SECTOR_NR GENMASK(15, 12) +#define ECC_ERROR_ADDRESS__SECTOR GENMASK(15, 12) #define ERR_CORRECTION_INFO 0x640 -#define ERR_CORRECTION_INFO__BYTEMASK GENMASK(7, 0) -#define ERR_CORRECTION_INFO__DEVICE_NR GENMASK(11, 8) -#define ERR_CORRECTION_INFO__ERROR_TYPE BIT(14) -#define ERR_CORRECTION_INFO__LAST_ERR_INFO BIT(15) +#define ERR_CORRECTION_INFO__BYTE GENMASK(7, 0) +#define ERR_CORRECTION_INFO__DEVICE GENMASK(11, 8) +#define ERR_CORRECTION_INFO__UNCOR BIT(14) +#define ERR_CORRECTION_INFO__LAST_ERR BIT(15) #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) #define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8)