From patchwork Sun Aug 20 10:10:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 110477 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp18751qge; Sun, 20 Aug 2017 03:11:41 -0700 (PDT) X-Received: by 10.84.129.69 with SMTP id 63mr16149267plb.117.1503223901348; Sun, 20 Aug 2017 03:11:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503223901; cv=none; d=google.com; s=arc-20160816; b=gFg8RVpPeNmUe8gQyEAoG8VuhE4SqQ525HnIzJ0QilaBUDox0Be1jrVKAkeZ1Ng9Xs xb15poUvdpLlw7E0DbOzW5191n7wkqCxkCA+7cHEZDGkixaSSZD31exR+B+DuAccAjgy eBOS+jfeGbp2CS8BMxU0g4ETSMUKKzVtjtS2kTZHt7YX69ezSrg6Xitqw3wx6lfLLp1L 4Aewc1VEYeln4JJ95zFNEqwEanwMlG3OnySuruHF+FpjnYYO23cV1hqLJkJLVyiUbRRF UuKCDT9s8NRS0crLRTHreUlK3xX7dgMBlG2451zm3dHFPzi5hwsRSR2CX1CNrammObLR yKFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=r6TSyti54c9OrdS2DDS2lzdbY3omzvS4Jz+ZhkYBEVI=; b=vwm+JKIixXJGsevSjo7wVcs6YOczjWlrVoAQfs6DTTLaZUKGxgrv0gY7ekxHe1F1pe 92vrTbd3nibhso98utEJSwvWw0unTMUfVseaz8OGVlIcryJMr3NXHSpBXhQEt+ra//dH tJe3Qt4LLjA2w7u/ThN7vD5klxL/qKRmXorWyNeE7+oOmeQfFmyZuDF9oPaCsKx06W+p U5ty3zzmEmEUYZw8YxwOSAcMvVBYpC/+Yx6c1y1PfjeURQbGIk0RmtBYoKtetV1CO4rN Be5GrKuLYvjR6W6Cfg7wEXrM8t56J9/lvPLAVfa0kn8/gInKjNWIwFHjvNFc+lhLEdFc 2NAA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i1si6578705plk.597.2017.08.20.03.11.41; Sun, 20 Aug 2017 03:11:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752754AbdHTKLX (ORCPT + 26 others); Sun, 20 Aug 2017 06:11:23 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:4515 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752253AbdHTKLU (ORCPT ); Sun, 20 Aug 2017 06:11:20 -0400 Received: from 172.30.72.60 (EHLO DGGEMS402-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFN22681; Sun, 20 Aug 2017 18:11:09 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.301.0; Sun, 20 Aug 2017 18:11:02 +0800 From: Ding Tianhong To: , , , , , , , , CC: Ding Tianhong Subject: [PATCH v3 net 2/2 RESEND] net: ixgbe: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Date: Sun, 20 Aug 2017 18:10:55 +0800 Message-ID: <1503223855-24616-3-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1503223855-24616-1-git-send-email-dingtianhong@huawei.com> References: <1503223855-24616-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.5999603E.003F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ba80bb68b9de4e136cddbfebdb00bdf0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ixgbe driver use the compile check to determine if it can send TLPs to Root Port with the Relaxed Ordering Attribute set, this is too inconvenient, now the new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING has been added to the kernel and we could check the bit4 in the PCIe Device Control register to determine whether we should use the Relaxed Ordering Attributes or not, so use this new way in the ixgbe driver. Signed-off-by: Ding Tianhong --- drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c | 22 ---------------------- drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 19 ------------------- 2 files changed, 41 deletions(-) -- 1.8.3.1 diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c index 523f9d0..8a32eb7 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c @@ -175,31 +175,9 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) **/ static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) { -#ifndef CONFIG_SPARC - u32 regval; - u32 i; -#endif s32 ret_val; ret_val = ixgbe_start_hw_generic(hw); - -#ifndef CONFIG_SPARC - /* Disable relaxed ordering */ - for (i = 0; ((i < hw->mac.max_tx_queues) && - (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { - regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); - regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; - IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); - } - - for (i = 0; ((i < hw->mac.max_rx_queues) && - (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { - regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); - regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | - IXGBE_DCA_RXCTRL_HEAD_WRO_EN); - IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); - } -#endif if (ret_val) return ret_val; diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c index d4933d2..96c324f 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c @@ -350,25 +350,6 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) } IXGBE_WRITE_FLUSH(hw); -#ifndef CONFIG_SPARC - /* Disable relaxed ordering */ - for (i = 0; i < hw->mac.max_tx_queues; i++) { - u32 regval; - - regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); - regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; - IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); - } - - for (i = 0; i < hw->mac.max_rx_queues; i++) { - u32 regval; - - regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); - regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | - IXGBE_DCA_RXCTRL_HEAD_WRO_EN); - IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); - } -#endif return 0; }