From patchwork Fri Aug 18 06:21:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 110358 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp498643qge; Thu, 17 Aug 2017 23:21:52 -0700 (PDT) X-Received: by 10.84.143.1 with SMTP id 1mr8814917ply.103.1503037312750; Thu, 17 Aug 2017 23:21:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503037312; cv=none; d=google.com; s=arc-20160816; b=D7AiSnW+PcmmsZMsKBGsPh1dpje+e3W2D9aQriHd1KmP2/mycj6pVURsnCh1HNYRjW XtOq5yMaqLj5bowQMCMX0YGZn3oeO2ic+Br9myFyzfm91JXgHuHin0H+hTAkbiw+vqLl hvDlVf4JaI5TYDcRVMb+uvZnc9KRElBn3MA22+OTZWB1EWFHquDW3QH7mtnTZh4wl8zR qZ36AxJps8QUHSL95nJdF//riLauHPj3ySsSLtd3TY3KVTWRrilrxn45xjnunItNFpkd pWVhKHABoetD5cyl2YvIf72qXNdaiPYWysDdRGfCxmIM7PcpS9DzXy3NFbal9W8jiPCq vkUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=r6TSyti54c9OrdS2DDS2lzdbY3omzvS4Jz+ZhkYBEVI=; b=FAKjdmzTjFgCQLTxMT7MyxnVE/dx/bvB4RO4FMkQrooaufduY9nEtu5zKvKR2ik1wg LSl2AnalNOWVYLjrNzGTCrqMpmXqa+6sr3zsJ2dZ+zutxIMqgS7u5oyeiELmMIKRYSgY VepEVmTcPAS8pMXxmHb/85gWPT46SaL6DGe1OtsUL71SkRu7lG+lZo1lxvqNQISNRGTI JrDjRTFCayVXZtkKW9c2BW1FSi1TdZrDvlavPs48RBtgioSbcJApgUmjndFLPYyaNsyo sJm98u0jnoegP7im3bf8t2Y6LgSLsbZ4q7H0tO6Vj/5m3Z1pdhtfxVC/Me6Gry3Pfxuu LqWg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p1si3422788pli.429.2017.08.17.23.21.52; Thu, 17 Aug 2017 23:21:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751786AbdHRGVf (ORCPT + 26 others); Fri, 18 Aug 2017 02:21:35 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:4065 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750905AbdHRGVa (ORCPT ); Fri, 18 Aug 2017 02:21:30 -0400 Received: from 172.30.72.60 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.60]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM12718; Fri, 18 Aug 2017 14:21:23 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 14:21:12 +0800 From: Ding Tianhong To: , , , , , , , , CC: Ding Tianhong Subject: [PATCH v3 net 2/2] net: ixgbe: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Date: Fri, 18 Aug 2017 14:21:05 +0800 Message-ID: <1503037265-11144-3-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1503037265-11144-1-git-send-email-dingtianhong@huawei.com> References: <1503037265-11144-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.59968763.00D7, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 5a3097fc7cc18c79f2dffba5c9431f73 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ixgbe driver use the compile check to determine if it can send TLPs to Root Port with the Relaxed Ordering Attribute set, this is too inconvenient, now the new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING has been added to the kernel and we could check the bit4 in the PCIe Device Control register to determine whether we should use the Relaxed Ordering Attributes or not, so use this new way in the ixgbe driver. Signed-off-by: Ding Tianhong --- drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c | 22 ---------------------- drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 19 ------------------- 2 files changed, 41 deletions(-) -- 1.8.3.1 Acked-by: Emil Tantilov diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c index 523f9d0..8a32eb7 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c @@ -175,31 +175,9 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) **/ static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) { -#ifndef CONFIG_SPARC - u32 regval; - u32 i; -#endif s32 ret_val; ret_val = ixgbe_start_hw_generic(hw); - -#ifndef CONFIG_SPARC - /* Disable relaxed ordering */ - for (i = 0; ((i < hw->mac.max_tx_queues) && - (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { - regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); - regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; - IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); - } - - for (i = 0; ((i < hw->mac.max_rx_queues) && - (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { - regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); - regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | - IXGBE_DCA_RXCTRL_HEAD_WRO_EN); - IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); - } -#endif if (ret_val) return ret_val; diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c index d4933d2..96c324f 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c @@ -350,25 +350,6 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) } IXGBE_WRITE_FLUSH(hw); -#ifndef CONFIG_SPARC - /* Disable relaxed ordering */ - for (i = 0; i < hw->mac.max_tx_queues; i++) { - u32 regval; - - regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); - regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; - IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); - } - - for (i = 0; i < hw->mac.max_rx_queues; i++) { - u32 regval; - - regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); - regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | - IXGBE_DCA_RXCTRL_HEAD_WRO_EN); - IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); - } -#endif return 0; }