From patchwork Tue Aug 15 06:26:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 110094 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp5114892obb; Mon, 14 Aug 2017 23:27:37 -0700 (PDT) X-Received: by 10.84.224.134 with SMTP id s6mr30875038plj.4.1502778457665; Mon, 14 Aug 2017 23:27:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502778457; cv=none; d=google.com; s=arc-20160816; b=Xh6c4oPMxSW2srgz5vbqu1NIzlxgaVbqDYELxyoa9fayzGyvg9kcXAPXTFRKNK0B7u NCgRPZ2hIZ7o7evY9RpoI6gJLtt6o/EjlLVQiWxYThJbF72/u9eE5Zh1wLlENTc0UCwY 8XgOm7/57YfSUd/7EbMg11MBVDSt6Tu9O9+/rImUre9P6N9dyWT4Lpxlw5cBLvZlMZ+r VatX16stJ1IlWNIwmNpGlW7CDry4XQKFg/F4OM/rmEjFDr+QOSLy+3CAzVYX/hc8rqtM cw+gciHQzTMqMz8+6ZvTc3wKqlmHuU9E8ZIRlwsqVJrnEHmkdXe0qrpiZJqLmC9DqpfD zjTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=ViBAtnrn8zH8a57llzMORLRKTorb01Q0h+gxhm3Ow7Q=; b=EiGKpD06pmMvxzUwjb/BSYBU9MC8dXrZgfKXzfTIjmOCfY+LWV985CpkiBsD5oaur9 CXaHEYRhX+2W29Gd2Skg6xYiQhot/YOLu57jdkpjfYAOOfSzvNfZmRrFKsPIUazCA4cM 2SDN3Ty6tduw9/Tsyf5+DiBX9MgaXJYsURJAgDGOPWB7BhOZWNc3I/VvWlFte3ndhqmM BdpWSF0d3R01sUDI0FwFS8jusLZE29QfeyzfS9UjAFSU0adYzqDWFvoBGNH3W8XzY5vk WvVajpBQpeLvZVnl6UzhfTBWhrSVwQ0Hd/IYmLW2I86T2YgsPc45917Vadw2fTjMxPVi gYWQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g6si5763883plm.924.2017.08.14.23.27.37; Mon, 14 Aug 2017 23:27:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753352AbdHOG1f (ORCPT + 25 others); Tue, 15 Aug 2017 02:27:35 -0400 Received: from foss.arm.com ([217.140.101.70]:48076 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753071AbdHOG1b (ORCPT ); Tue, 15 Aug 2017 02:27:31 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3354B2B; Mon, 14 Aug 2017 23:27:31 -0700 (PDT) Received: from gby.kfn.arm.com (unknown [10.45.48.148]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9418F3F3E1; Mon, 14 Aug 2017 23:27:29 -0700 (PDT) From: Gilad Ben-Yossef To: Greg Kroah-Hartman , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Cc: Ofir Drang Subject: [PATCH v3 06/22] staging: ccree: simplify resource release on error Date: Tue, 15 Aug 2017 09:26:34 +0300 Message-Id: <1502778412-16255-7-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1502778412-16255-1-git-send-email-gilad@benyossef.com> References: <1502778412-16255-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The resource release on probe/init error was being handled in an awkward manner and possibly leaking memory on certain (unlikely) error path. Fix it by simplifying the error resource release and making it easier to track. Reported-by: Dan Carpenter Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_aead.c | 3 +- drivers/staging/ccree/ssi_cipher.c | 3 +- drivers/staging/ccree/ssi_driver.c | 102 ++++++++++++++++++++----------------- drivers/staging/ccree/ssi_hash.c | 3 +- 4 files changed, 59 insertions(+), 52 deletions(-) -- 2.1.4 diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c index a8cb432..66eedbe 100644 --- a/drivers/staging/ccree/ssi_aead.c +++ b/drivers/staging/ccree/ssi_aead.c @@ -2719,6 +2719,7 @@ int ssi_aead_alloc(struct ssi_drvdata *drvdata) goto fail0; } + INIT_LIST_HEAD(&aead_handle->aead_list); drvdata->aead_handle = aead_handle; aead_handle->sram_workspace_addr = ssi_sram_mgr_alloc( @@ -2729,8 +2730,6 @@ int ssi_aead_alloc(struct ssi_drvdata *drvdata) goto fail1; } - INIT_LIST_HEAD(&aead_handle->aead_list); - /* Linux crypto */ for (alg = 0; alg < ARRAY_SIZE(aead_algs); alg++) { t_alg = ssi_aead_create_alg(&aead_algs[alg]); diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c index d98178d..712b21d 100644 --- a/drivers/staging/ccree/ssi_cipher.c +++ b/drivers/staging/ccree/ssi_cipher.c @@ -1281,9 +1281,8 @@ int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata) if (!ablkcipher_handle) return -ENOMEM; - drvdata->blkcipher_handle = ablkcipher_handle; - INIT_LIST_HEAD(&ablkcipher_handle->blkcipher_alg_list); + drvdata->blkcipher_handle = ablkcipher_handle; /* Linux crypto */ SSI_LOG_DEBUG("Number of algorithms = %zu\n", ARRAY_SIZE(blkcipher_algs)); diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c index c18e7e3..1b95f90 100644 --- a/drivers/staging/ccree/ssi_driver.c +++ b/drivers/staging/ccree/ssi_driver.c @@ -233,16 +233,14 @@ static int init_cc_resources(struct platform_device *plat_dev) if (!new_drvdata) { SSI_LOG_ERR("Failed to allocate drvdata"); rc = -ENOMEM; - goto init_cc_res_err; + goto post_drvdata_err; } + dev_set_drvdata(&plat_dev->dev, new_drvdata); + new_drvdata->plat_dev = plat_dev; new_drvdata->clk = of_clk_get(np, 0); new_drvdata->coherent = of_dma_is_coherent(np); - /*Initialize inflight counter used in dx_ablkcipher_secure_complete used for count of BYSPASS blocks operations*/ - new_drvdata->inflight_counter = 0; - - dev_set_drvdata(&plat_dev->dev, new_drvdata); /* Get device resources */ /* First CC registers space */ req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); @@ -250,38 +248,42 @@ static int init_cc_resources(struct platform_device *plat_dev) new_drvdata->cc_base = devm_ioremap_resource(&plat_dev->dev, req_mem_cc_regs); if (IS_ERR(new_drvdata->cc_base)) { + SSI_LOG_ERR("Failed to ioremap registers"); rc = PTR_ERR(new_drvdata->cc_base); - goto init_cc_res_err; + goto post_drvdata_err; } + SSI_LOG_DEBUG("Got MEM resource (%s): start=%pad end=%pad\n", req_mem_cc_regs->name, req_mem_cc_regs->start, req_mem_cc_regs->end); SSI_LOG_DEBUG("CC registers mapped from %pa to 0x%p\n", &req_mem_cc_regs->start, new_drvdata->cc_base); + cc_base = new_drvdata->cc_base; + /* Then IRQ */ new_drvdata->irq = platform_get_irq(plat_dev, 0); if (new_drvdata->irq < 0) { SSI_LOG_ERR("Failed getting IRQ resource\n"); rc = new_drvdata->irq; - goto init_cc_res_err; + goto post_drvdata_err; } + rc = devm_request_irq(&plat_dev->dev, new_drvdata->irq, cc_isr, IRQF_SHARED, "arm_cc7x", new_drvdata); if (rc) { SSI_LOG_ERR("Could not register to interrupt %d\n", new_drvdata->irq); - goto init_cc_res_err; + goto post_drvdata_err; } - init_completion(&new_drvdata->icache_setup_completion); - SSI_LOG_DEBUG("Registered to IRQ: %d\n", new_drvdata->irq); - new_drvdata->plat_dev = plat_dev; + + init_completion(&new_drvdata->icache_setup_completion); rc = cc_clk_on(new_drvdata); if (rc) - goto init_cc_res_err; + goto post_drvdata_err; if (!new_drvdata->plat_dev->dev.dma_mask) new_drvdata->plat_dev->dev.dma_mask = &new_drvdata->plat_dev->dev.coherent_dma_mask; @@ -295,7 +297,7 @@ static int init_cc_resources(struct platform_device *plat_dev) SSI_LOG_ERR("Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n", signature_val, (u32)DX_DEV_SIGNATURE); rc = -EINVAL; - goto init_cc_res_err; + goto post_clk_err; } SSI_LOG_DEBUG("CC SIGNATURE=0x%08X\n", signature_val); @@ -306,21 +308,26 @@ static int init_cc_resources(struct platform_device *plat_dev) rc = init_cc_regs(new_drvdata, true); if (unlikely(rc != 0)) { SSI_LOG_ERR("init_cc_regs failed\n"); - goto init_cc_res_err; + goto post_clk_err; } #ifdef ENABLE_CC_SYSFS rc = ssi_sysfs_init(&plat_dev->dev.kobj, new_drvdata); if (unlikely(rc != 0)) { SSI_LOG_ERR("init_stat_db failed\n"); - goto init_cc_res_err; + goto post_regs_err; } #endif + rc = ssi_fips_init(new_drvdata); + if (unlikely(rc != 0)) { + SSI_LOG_ERR("SSI_FIPS_INIT failed 0x%x\n", rc); + goto post_sysfs_err; + } rc = ssi_sram_mgr_init(new_drvdata); if (unlikely(rc != 0)) { SSI_LOG_ERR("ssi_sram_mgr_init failed\n"); - goto init_cc_res_err; + goto post_fips_init_err; } new_drvdata->mlli_sram_addr = @@ -328,57 +335,51 @@ static int init_cc_resources(struct platform_device *plat_dev) if (unlikely(new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR)) { SSI_LOG_ERR("Failed to alloc MLLI Sram buffer\n"); rc = -ENOMEM; - goto init_cc_res_err; + goto post_sram_mgr_err; } rc = request_mgr_init(new_drvdata); if (unlikely(rc != 0)) { SSI_LOG_ERR("request_mgr_init failed\n"); - goto init_cc_res_err; + goto post_sram_mgr_err; } rc = ssi_buffer_mgr_init(new_drvdata); if (unlikely(rc != 0)) { SSI_LOG_ERR("buffer_mgr_init failed\n"); - goto init_cc_res_err; + goto post_req_mgr_err; } rc = ssi_power_mgr_init(new_drvdata); if (unlikely(rc != 0)) { SSI_LOG_ERR("ssi_power_mgr_init failed\n"); - goto init_cc_res_err; - } - - rc = ssi_fips_init(new_drvdata); - if (unlikely(rc != 0)) { - SSI_LOG_ERR("SSI_FIPS_INIT failed 0x%x\n", rc); - goto init_cc_res_err; + goto post_buf_mgr_err; } rc = ssi_ivgen_init(new_drvdata); if (unlikely(rc != 0)) { SSI_LOG_ERR("ssi_ivgen_init failed\n"); - goto init_cc_res_err; + goto post_power_mgr_err; } /* Allocate crypto algs */ rc = ssi_ablkcipher_alloc(new_drvdata); if (unlikely(rc != 0)) { SSI_LOG_ERR("ssi_ablkcipher_alloc failed\n"); - goto init_cc_res_err; + goto post_ivgen_err; } /* hash must be allocated before aead since hash exports APIs */ rc = ssi_hash_alloc(new_drvdata); if (unlikely(rc != 0)) { SSI_LOG_ERR("ssi_hash_alloc failed\n"); - goto init_cc_res_err; + goto post_cipher_err; } rc = ssi_aead_alloc(new_drvdata); if (unlikely(rc != 0)) { SSI_LOG_ERR("ssi_aead_alloc failed\n"); - goto init_cc_res_err; + goto post_hash_err; } /* If we got here and FIPS mode is enabled @@ -389,24 +390,33 @@ static int init_cc_resources(struct platform_device *plat_dev) return 0; -init_cc_res_err: - SSI_LOG_ERR("Freeing CC HW resources!\n"); - - if (new_drvdata) { - ssi_aead_free(new_drvdata); - ssi_hash_free(new_drvdata); - ssi_ablkcipher_free(new_drvdata); - ssi_ivgen_fini(new_drvdata); - ssi_power_mgr_fini(new_drvdata); - ssi_buffer_mgr_fini(new_drvdata); - request_mgr_fini(new_drvdata); - ssi_sram_mgr_fini(new_drvdata); - ssi_fips_fini(new_drvdata); +post_hash_err: + ssi_hash_free(new_drvdata); +post_cipher_err: + ssi_ablkcipher_free(new_drvdata); +post_ivgen_err: + ssi_ivgen_fini(new_drvdata); +post_power_mgr_err: + ssi_power_mgr_fini(new_drvdata); +post_buf_mgr_err: + ssi_buffer_mgr_fini(new_drvdata); +post_req_mgr_err: + request_mgr_fini(new_drvdata); +post_sram_mgr_err: + ssi_sram_mgr_fini(new_drvdata); +post_fips_init_err: + ssi_fips_fini(new_drvdata); +post_sysfs_err: #ifdef ENABLE_CC_SYSFS - ssi_sysfs_fini(); + ssi_sysfs_fini(); #endif - dev_set_drvdata(&plat_dev->dev, NULL); - } +post_regs_err: + fini_cc_regs(new_drvdata); +post_clk_err: + cc_clk_off(new_drvdata); +post_drvdata_err: + SSI_LOG_ERR("ccree init error occurred!\n"); + dev_set_drvdata(&plat_dev->dev, NULL); return rc; } diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c index 6c08b1d..3e7873c 100644 --- a/drivers/staging/ccree/ssi_hash.c +++ b/drivers/staging/ccree/ssi_hash.c @@ -2229,6 +2229,7 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) goto fail; } + INIT_LIST_HEAD(&hash_handle->hash_list); drvdata->hash_handle = hash_handle; sram_size_to_alloc = sizeof(digest_len_init) + @@ -2259,8 +2260,6 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) goto fail; } - INIT_LIST_HEAD(&hash_handle->hash_list); - /* ahash registration */ for (alg = 0; alg < ARRAY_SIZE(driver_hash); alg++) { struct ssi_hash_alg *t_alg;