From patchwork Tue Aug 15 03:23:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 110075 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp5156130qge; Mon, 14 Aug 2017 20:25:00 -0700 (PDT) X-Received: by 10.84.160.226 with SMTP id v31mr29138868plg.91.1502767499901; Mon, 14 Aug 2017 20:24:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502767499; cv=none; d=google.com; s=arc-20160816; b=FRQidbtFDrv/5JqINUEA+HQFQqAOswXW4djB4qscxA5UeCi/puBFjM3QT8BxxpTX27 Nrcpxae2CkNsqgfkIMiE34MJZq5VE5zHbhQpzKAM38qQZ6u1FBpE7AkW0U7jGDE6KDVP X7SIC0LNF+ocbTYNnw92NNPzrlOzUZFHTTSE7XaO2PCb0kLZ7v0m7JZ2EENPoG+Ag4EK HLmYDCLJ0xVKI1eIuK87Q38ruc4r3udEG+KFcLWTl7KfWTbWyRmtr6iE/cWjqx3jUrcc IPcNJLiTcgARmSFxEN8jxyeSxryJRgav33sGr24wi41cxq0vrNmRGl1LsdOJ4BA0jr3h 3GQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=VppCJV33XL8JaCppBVkNbuKtOsPWQHMiNOLA8nzHZy8=; b=Rgc17yNfE2TX+EYaSe2c1iBf/5hv9meJM7BzUql8yH/WQNfmJVl2iOf3Lg0VeAEDLE UUxLYIi5LPuuI/UAtJzkAypsmzcI5vp7DIMAtidPOV2Dhh2GxAEfxtoGd6P+a++ZpJ1/ Pu0aznZ9N0vTyiL84awV6o0m/WlGMv8OzcBcL5ejNuErMNRwnGBhXtTJOx+xGo0CWSUS Tljl1x6FlgR87lF1Z60MhVycam3e9sD4vCpQxV0ddOTY8nJPEJYnVlEAZCzWcMXoIYTC B3eEI7G/oC/NPnYjH20Zbn/awiJdkftvDn7Sgd6bbcM0gpPmlL9fIwN2PhuEE4MZVORe JBWA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l61si5531522plb.86.2017.08.14.20.24.59; Mon, 14 Aug 2017 20:24:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753271AbdHODYE (ORCPT + 25 others); Mon, 14 Aug 2017 23:24:04 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:3521 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753148AbdHODYC (ORCPT ); Mon, 14 Aug 2017 23:24:02 -0400 Received: from 172.30.72.60 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFE31821; Tue, 15 Aug 2017 11:23:46 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Tue, 15 Aug 2017 11:23:38 +0800 From: Ding Tianhong To: , , , , , , , , , , , , , , , , , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v11 3/5] PCI: Disable Relaxed Ordering Attributes for AMD A1100 Date: Tue, 15 Aug 2017 11:23:25 +0800 Message-ID: <1502767407-6812-4-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1502767407-6812-1-git-send-email-dingtianhong@huawei.com> References: <1502767407-6812-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A010203.59926944.0033, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 9d64640c013596b1bc4e3fcb966edf67 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Casey reported that the AMD ARM A1100 SoC has a bug in its PCIe Root Port where Upstream Transaction Layer Packets with the Relaxed Ordering Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering set, it would cause Data Corruption, so we need to disable Relaxed Ordering Attribute when Upstream TLPs to the Root Port. Reported-and-suggested-by: Casey Leedom Signed-off-by: Casey Leedom Signed-off-by: Ding Tianhong Acked-by: Casey Leedom --- drivers/pci/quirks.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 1.8.3.1 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 1272f7e..1407604 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4089,6 +4089,22 @@ static void quirk_relaxedordering_disable(struct pci_dev *dev) quirk_relaxedordering_disable); /* + * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex + * where Upstream Transaction Layer Packets with the Relaxed Ordering + * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering + * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules + * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 + * November 10, 2010). As a result, on this platform we can't use Relaxed + * Ordering for Upstream TLPs. + */ +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); + +/* * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same * values for the Attribute as were supplied in the header of the * corresponding Request, except as explicitly allowed when IDO is used."