From patchwork Mon Aug 14 15:44:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 110053 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp4505662qge; Mon, 14 Aug 2017 08:47:51 -0700 (PDT) X-Received: by 10.98.2.146 with SMTP id 140mr13096655pfc.207.1502725671237; Mon, 14 Aug 2017 08:47:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502725671; cv=none; d=google.com; s=arc-20160816; b=EIzeTb/z42Tjqr5HhhITU75Sy1Btpq05vHeU9Y2Xqm2qdfZIJyAF22y93kSVMznPrk UGhmS7Jz1CwrfIy01PvH8sGig/AHiTTXB6bdh15US3x6OM63pQAIQEFp7u8Ccm+LvIyy byFmBsZHuYJOdRb4ubJ+wXWDLtDe/5wWlmWdzPswdRtINeenQMcXZcZiLpxFPX7tEk5h nHqp9wp26eyxDR/rr2oHne/oOD0J8hg5r6YALV8nWWTFZfIWEouQt7C+R61TaF7Uss52 d1Y0AYjR1YWQRqS5y3jnIyVAM0HwyUdlDM8iymCt34cN0pfbRBU4xAvMC9EbXYMcmjec Tj5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=Tvw2aoHTNt/zpbHFmgbucgjJLnxgnvUS4rsp1LMKR84=; b=xhPeD6I0cIKGf/zZNtrCSGBOXyoA8DTR1lpfEUJxOsQrEAHMKeRT9yRfqtjWESnoFQ t5whnRYoluBMvxVKOQaVIe8YlXvB4AsKaUSSyn86W2+fHOVZatwlKrS/k9G2a7Hm80Ca mYVIXxdMCxGUAE+FZdJLG9JAmHYmDMwBUETkkIyH7NkUDshRzA0ChiI/ZPKVDaTeYWnV 2dfYNcFn03Zpq5HDFS552h4b5pBMVzVAxtP9yhJKeGm2ABY/Vm5AMHjO558paWBdY+vb pUh3Jw+UoNjWyFw2IDGPoyWnMsujt3xqAbl1PykxfT3lkIVRDYaPTAclGwnrzPA42Kkk 4mcA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g15si4791744pli.354.2017.08.14.08.47.50; Mon, 14 Aug 2017 08:47:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753277AbdHNPrs (ORCPT + 25 others); Mon, 14 Aug 2017 11:47:48 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:3080 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751441AbdHNPpb (ORCPT ); Mon, 14 Aug 2017 11:45:31 -0400 Received: from 172.30.72.60 (EHLO DGGEMS408-HUB.china.huawei.com) ([172.30.72.60]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFF55872; Mon, 14 Aug 2017 23:45:16 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.301.0; Mon, 14 Aug 2017 23:45:06 +0800 From: Ding Tianhong To: , , , , , , , , , , , , , , , , , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v10 3/5] PCI: Disable Relaxed Ordering Attributes for AMD A1100 Date: Mon, 14 Aug 2017 23:44:57 +0800 Message-ID: <1502725499-11276-4-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1502725499-11276-1-git-send-email-dingtianhong@huawei.com> References: <1502725499-11276-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.5991C58C.008D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 788d57bf3a183630211b9dd3dd73331c Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Casey reported that the AMD ARM A1100 SoC has a bug in its PCIe Root Port where Upstream Transaction Layer Packets with the Relaxed Ordering Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering set, it would cause Data Corruption, so we need to disable Relaxed Ordering Attribute when Upstream TLPs to the Root Port. Signed-off-by: Casey Leedom Signed-off-by: Ding Tianhong Acked-by: Alexander Duyck Acked-by: Ashok Raj --- drivers/pci/quirks.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 1.8.3.1 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 1272f7e..1407604 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4089,6 +4089,22 @@ static void quirk_relaxedordering_disable(struct pci_dev *dev) quirk_relaxedordering_disable); /* + * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex + * where Upstream Transaction Layer Packets with the Relaxed Ordering + * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering + * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules + * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 + * November 10, 2010). As a result, on this platform we can't use Relaxed + * Ordering for Upstream TLPs. + */ +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); + +/* * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same * values for the Attribute as were supplied in the header of the * corresponding Request, except as explicitly allowed when IDO is used."