From patchwork Thu Aug 3 13:44:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 109343 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp15492obb; Thu, 3 Aug 2017 06:47:38 -0700 (PDT) X-Received: by 10.84.237.15 with SMTP id s15mr2140869plk.100.1501768057915; Thu, 03 Aug 2017 06:47:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501768057; cv=none; d=google.com; s=arc-20160816; b=N6sZI25waFd+bc4Ag/Lprbf7qYfrI5gaJ1HmG5zdLklHqqKdyadZHtyrjQQe8/FV2z kPm4QXUPvasyMY4Iuwae7brFdVZtSPhe7soUhOCA6SHi1l37bGX8rRx/MJNyWgIAP95u UFVZKllwiBlZKQTSoBJy106bnwNqW9w/JnW8/dy3qkWIAv7bc6M73U/dvJ8lva+QNAF4 jpAiRa4a+vVyF+mbBceI3j8x+qI3LVpJx/qS8OQII62/Xr3TROJgpQEljyEaPJ6aYORY orQck0gTstW46KdCwSjZXGtYdYWy+aCz8QIXtwKeL1Uj5n/5DMQv8E41wCaUIlFFEFTj 3ImA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=m3FJuPpj8A+eXIbdja6kZWtiJ814O8xZhxwvR/u9Zis=; b=y0+5Mt+XHTdsjJ1sYYEY/3sx0MAmzdStp8/b9rJTxplqQFPTbsmDDGTeY5suZPm3p1 9tdO4EyqwOAgdQ5ZDTN9A+dcsWJglflnnIcvyFHGqMCkeUP8nxuPmx9K5/mFHC47MwX2 1KtZVYFQSUeXnKbl16AJJ/AOKy1xZSW2gwB6gBqci6kSPVdbMVNiR7hx0dbtEIqYVGo+ Sh1aB68dcBgB0ydrt4sCqMu4EHzw+woXndDkmK0OgOWbZXPU0sEt5lajIQRic3SeYZWa 1EZkNYXDlUEA8+dz5XmsMdEntm1yuYUMwUjEK2/5OFlzyxG1GjRGY5TZIEL4uRfSeTaO vIiw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b65si7595866pgc.1.2017.08.03.06.47.36; Thu, 03 Aug 2017 06:47:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752097AbdHCNre (ORCPT + 25 others); Thu, 3 Aug 2017 09:47:34 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:9919 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751220AbdHCNpk (ORCPT ); Thu, 3 Aug 2017 09:45:40 -0400 Received: from 172.30.72.55 (EHLO DGGEML401-HUB.china.huawei.com) ([172.30.72.55]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASU39382; Thu, 03 Aug 2017 21:45:18 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEML401-HUB.china.huawei.com (10.3.17.32) with Microsoft SMTP Server id 14.3.301.0; Thu, 3 Aug 2017 21:45:07 +0800 From: Ding Tianhong To: , , , , , , , , , , , , , , , , , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v8 1/4] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING Date: Thu, 3 Aug 2017 21:44:46 +0800 Message-ID: <1501767889-7772-2-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1501767889-7772-1-git-send-email-dingtianhong@huawei.com> References: <1501767889-7772-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0201.598328F1.015B, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d9f5f711b66c40be2efb1e52a7186fff Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Casey Leedom The patch adds a new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING to indicate that Relaxed Ordering (RO) attribute should not be used for Transaction Layer Packets (TLP) targetted towards these affected root complexes. Current list of affected parts include Intel E5-26xx root complex which suffers from flow control credits that result in performance issues. On these affected parts RO can still be used for peer-2-peer traffic. AMD A1100 ARM ("SEATTLE") Root complexes don't obey PCIe 3.0 ordering rules, hence could lead to data-corruption. Signed-off-by: Casey Leedom Signed-off-by: Ding Tianhong Acked-by: Ashok Raj --- drivers/pci/quirks.c | 38 ++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 2 ++ 2 files changed, 40 insertions(+) -- 1.8.3.1 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 6967c6b..1e1cdbe 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4016,6 +4016,44 @@ static void quirk_tw686x_class(struct pci_dev *pdev) quirk_tw686x_class); /* + * Some devices have problems with Transaction Layer Packets with the Relaxed + * Ordering Attribute set. Such devices should mark themselves and other + * Device Drivers should check before sending TLPs with RO set. + */ +static void quirk_relaxedordering_disable(struct pci_dev *dev) +{ + dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; +} + +/* + * Intel E5-26xx Root Complex has a Flow Control Credit issue which can + * cause performance problems with Upstream Transaction Layer Packets with + * Relaxed Ordering set. + */ +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); + +/* + * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex + * where Upstream Transaction Layer Packets with the Relaxed Ordering + * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering + * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules + * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 + * November 10, 2010). As a result, on this platform we can't use Relaxed + * Ordering for Upstream TLPs. + */ +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); + +/* * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same * values for the Attribute as were supplied in the header of the * corresponding Request, except as explicitly allowed when IDO is used." diff --git a/include/linux/pci.h b/include/linux/pci.h index 4869e66..412ec1c 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -188,6 +188,8 @@ enum pci_dev_flags { * the direct_complete optimization. */ PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11), + /* Don't use Relaxed Ordering for TLPs directed at this device */ + PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12), }; enum pci_irq_reroute_variant {