From patchwork Mon Jul 31 06:21:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 108976 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1916552qge; Sun, 30 Jul 2017 23:24:34 -0700 (PDT) X-Received: by 10.99.140.76 with SMTP id q12mr12940618pgn.45.1501482274421; Sun, 30 Jul 2017 23:24:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501482274; cv=none; d=google.com; s=arc-20160816; b=Bk37t7cmMifQFsONoEZZyhJ66rhcdpzPXhv0I/GC5+89eYPqL31KVG/f/HgHNqMzzY hpfTdTGlazqTTpKiiPdSxhqQ7J7G+ugAwS/JngsRleMTmfiTWOMJUEm6QJ8VctWyBNWF P226VytMfiowsIMDQ4afPeDXX5w4JlKgna652ZDbTSKOexdUMj569X41xHQttNJ81cin Bl4wa/F+fmbBINUbErNfz3wnlHHtgWI5xmZmDNuWr/HsAg/raWfS12TGLHvrYhgJsgC8 zpDFKhtpXx3tfv1Q0Bq7MDKbHSoe+Eqc+FOmaJ3HIkFahY7+l3sbjG4QSGezRROIqHKd Bs+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=q/p8CbcQsoho1ayP9lJ2n4DZUgHY8rsBJbDYDSTW4AE=; b=UGYceSzW+J9kqqABWyr6lj8cl1R+UKylqOWoTghHBZVfC7doRxHbB+OIpZSHzttZVz P0uz2O7AG+10t4XnBzTCDIBpTj1ib/yqkSov0MGLz42evY8spBq7nlCLGzdiLoV9FF+C endse1CRHR8ehJ7ye5EjQgw57DJKa0bOFOwg3x2VAh0iz4bKE7Z0Imm+k/445fHUIN4l 1dSDKVzhWejzuolvYRSklBYLPh7itD+DF6ghOybeexfGwcdoEO0lH7Afe3ZGioPkfazR 6FCzUkgn8OGSgLwIK+lGmT0CCufxuPIjk3XYYyLUZJONv3tYm2WBAu/2rxzB76ytnpaC 11/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.b=RYFuAVoY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v6si17114184plk.103.2017.07.30.23.24.33; Sun, 30 Jul 2017 23:24:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.b=RYFuAVoY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751918AbdGaGYb (ORCPT + 26 others); Mon, 31 Jul 2017 02:24:31 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:41390 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750987AbdGaGXH (ORCPT ); Mon, 31 Jul 2017 02:23:07 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id v6V6M3A3000955; Mon, 31 Jul 2017 15:22:06 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v6V6M3A3000955 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1501482127; bh=q/p8CbcQsoho1ayP9lJ2n4DZUgHY8rsBJbDYDSTW4AE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RYFuAVoY7xXw1+QfBa7a66axR5yE5CqSy1le2meG9i/YK8mWJOW6rxwYhvDerxv4U Sp3T4vrYO7HrG0euhPSPtsru+dGt7+hnwSel1oWhbKdAE9pNi5d7VFkfdwhGsFntIb +Z50v4XGR4mCLqs4zDBkIopJrbwLc7Kkdr6/qE+SqNsRsX/Qwlhq+50dWyVNLhylf0 8cXxLuyqwhMMdt4LNs2iorZdyxvZqt8Ky1+kHDMfTyj4BsL1IGNbFA5NFDfkVVnXbM B1YAHn3NCPO1ucBg0rxUwKDAIq2pc7eJPqRVuFKm0/pisWQZOpZ5sTs1KKSMjL2I2c 3G+NjYfwfN+tQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-gpio@vger.kernel.org Cc: Masahiro Yamada , Linus Walleij , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] pinctrl: uniphier: fix pin_config_get() for input-enable Date: Mon, 31 Jul 2017 15:21:07 +0900 Message-Id: <1501482071-9819-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501482071-9819-1-git-send-email-yamada.masahiro@socionext.com> References: <1501482071-9819-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For LD11/LD20 SoCs (capable of per-pin input enable), iectrl bits are located across multiple registers. So, the register offset must be taken into account. Otherwise, wrong input-enable status is displayed. While we here, rename the macro because it is a base address. Fixes: aa543888ca8c ("pinctrl: uniphier: support per-pin input enable for new SoCs") Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index c649e835bd54..f2f0f9dcfec3 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -32,7 +32,7 @@ #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900 #define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00 -#define UNIPHIER_PINCTRL_IECTRL 0x1d00 +#define UNIPHIER_PINCTRL_IECTRL_BASE 0x1d00 struct uniphier_pinctrl_priv { struct pinctrl_desc pctldesc; @@ -252,18 +252,21 @@ static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev, { struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data); - unsigned int val; + unsigned int reg, mask, val; int ret; if (iectrl == UNIPHIER_PIN_IECTRL_NONE) /* This pin is always input-enabled. */ return 0; - ret = regmap_read(priv->regmap, UNIPHIER_PINCTRL_IECTRL, &val); + reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4; + mask = BIT(iectrl % 32); + + ret = regmap_read(priv->regmap, reg, &val); if (ret) return ret; - return val & BIT(iectrl) ? 0 : -EINVAL; + return val & mask ? 0 : -EINVAL; } static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev, @@ -456,7 +459,7 @@ static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev, if (iectrl == UNIPHIER_PIN_IECTRL_NONE) return enable ? 0 : -EINVAL; - reg = UNIPHIER_PINCTRL_IECTRL + iectrl / 32 * 4; + reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4; mask = BIT(iectrl % 32); return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0);