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[2607:f8b0:400e:c05::22e]) by mx.google.com with ESMTPS id p18si3551680pge.579.2017.07.21.14.26.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Jul 2017 14:26:21 -0700 (PDT) Received-SPF: pass (google.com: domain of john.stultz@linaro.org designates 2607:f8b0:400e:c05::22e as permitted sender) client-ip=2607:f8b0:400e:c05::22e; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=YRI8Ww/S; spf=pass (google.com: domain of john.stultz@linaro.org designates 2607:f8b0:400e:c05::22e as permitted sender) smtp.mailfrom=john.stultz@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by mail-pg0-x22e.google.com with SMTP id v190so33359019pgv.2 for ; Fri, 21 Jul 2017 14:26:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ed6r9nZCgA39uiWMWPDFJLlDxRhlQxuVyLKYm5ld/EM=; b=YRI8Ww/SM2MSgPc+nR8DCq/BtrZN0GZguOAmhfkoRB+wfTr+J4pimhCuBrgMGhEJQj swFMMKfJhmv5rmPbgbF/LSZVFDvWUwKAFlNF43OyI9/uzgKFagE9QDZTWDg3r5nWkccr 7swRHg05alrV3eRMNNil/ubdzwugfy+vcN+uo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ed6r9nZCgA39uiWMWPDFJLlDxRhlQxuVyLKYm5ld/EM=; b=gBleL0E9xXgjOdHq6b5PxGpMBT+qRiwq3H3ixm0cNuuLt6Aqebl3qUqI3BV5AnQRx/ ABlUBd98gcfYnXYrPh9rlcTw5kpgmNtyWV1MC5mm9T0LLH+L0xWeWqDsYggqG5LGDgFJ DKIdq7uMZpKM+p4AIQykECiz6EtOlMq5S8Lu/SvoucruyWhgLtj6uzf8wki73gInrnO6 FMldGkbxy+YWxLNFHtffJ+qVjP9WT2e1FddPkUIVjS+6tBT7nP1LYilir5KwVT7/IdPX 3PR5zUMQAseA6squjPU3enmiI8dNSpeEFYEiMKjo94W1B/F9y0xW6FUAK3M5U/6yuH1X mLaQ== X-Gm-Message-State: AIVw1125zxKiKGUF5BWugRWLgxW0FlQxSef8kXTC+Bqn9Mb6R1T8lkW9 XpNdynMKgZ15kyXTO9k= X-Received: by 10.98.138.197 with SMTP id o66mr3970125pfk.207.1500672380629; Fri, 21 Jul 2017 14:26:20 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([2601:1c2:1002:83f0:4e72:b9ff:fe99:466a]) by smtp.gmail.com with ESMTPSA id 16sm7522826pfq.151.2017.07.21.14.26.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 21 Jul 2017 14:26:19 -0700 (PDT) From: John Stultz To: lkml Cc: John Stultz , Daniel Vetter , Jani Nikula , Sean Paul , David Airlie , Rob Clark , Xinliang Liu , Xinliang Liu , Rongrong Zou , Xinwei Kong , Chen Feng , Jose Abreu , Archit Taneja , dri-devel@lists.freedesktop.org Subject: [RFC][PATCH v4] drm: kirin: Add mode_valid logic to avoid mode clocks we can't generate Date: Fri, 21 Jul 2017 14:26:15 -0700 Message-Id: <1500672375-26198-1-git-send-email-john.stultz@linaro.org> X-Mailer: git-send-email 2.7.4 Currently the hikey dsi logic cannot generate accurate byte clocks values for all pixel clock values. Thus if a mode clock is selected that cannot match the calculated byte clock, the device will boot with a blank screen. This patch uses the new mode_valid callback (many thanks to Jose Abreu for upstreaming it!) to ensure we don't select modes we cannot generate. Also, since the ade crtc code will adjust the mode in mode_set, this patch also adds a mode_fixup callback which we use to make sure we are validating the mode clock that will eventually be used. Cc: Daniel Vetter Cc: Jani Nikula Cc: Sean Paul Cc: David Airlie Cc: Rob Clark Cc: Xinliang Liu Cc: Xinliang Liu Cc: Rongrong Zou Cc: Xinwei Kong Cc: Chen Feng Cc: Jose Abreu Cc: Archit Taneja Cc: dri-devel@lists.freedesktop.org Signed-off-by: John Stultz --- v2: Reworked to calculate if modeclock matches the phy's byteclock, rather then using a whitelist of known modes. v3: Reworked to check across all possible crtcs (even though for us there is only one), and use mode_fixup instead of a custom function, as suggested by Jose and Daniel. v4: Fixes and improved error handling as suggested by Jose. --- drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 67 +++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 14 ++++++ 2 files changed, 81 insertions(+) -- 2.7.4 diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c index f77dcfa..043a50d 100644 --- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c @@ -603,6 +603,72 @@ static void dsi_encoder_enable(struct drm_encoder *encoder) dsi->enable = true; } +static enum drm_mode_status dsi_encoder_phy_mode_valid( + struct drm_encoder *encoder, + const struct drm_display_mode *mode) +{ + struct dw_dsi *dsi = encoder_to_dsi(encoder); + struct mipi_phy_params phy; + u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + u32 req_kHz, act_kHz, lane_byte_clk_kHz; + + /* Calculate the lane byte clk using the adjusted mode clk */ + memset(&phy, 0, sizeof(phy)); + req_kHz = mode->clock * bpp / dsi->lanes; + act_kHz = dsi_calc_phy_rate(req_kHz, &phy); + lane_byte_clk_kHz = act_kHz / 8; + + DRM_DEBUG_DRIVER("Checking mode %ix%i-%i@%i clock: %i...", + mode->hdisplay, mode->vdisplay, bpp, + drm_mode_vrefresh(mode), mode->clock); + + /* + * Make sure the adjused mode clock and the lane byte clk + * have a common denominator base frequency + */ + if (mode->clock/dsi->lanes == lane_byte_clk_kHz/3) { + DRM_DEBUG_DRIVER("OK!\n"); + return MODE_OK; + } + + DRM_DEBUG_DRIVER("BAD!\n"); + return MODE_BAD; +} + +static enum drm_mode_status dsi_encoder_mode_valid(struct drm_encoder *encoder, + const struct drm_display_mode *mode) + +{ + const struct drm_crtc_helper_funcs *crtc_funcs = NULL; + struct drm_crtc *crtc = NULL; + struct drm_display_mode adj_mode; + enum drm_mode_status ret; + + /* + * The crtc might adjust the mode, so go through the + * possible crtcs (technically just one) and call + * mode_fixup to figure out the adjusted mode before we + * validate it. + */ + drm_for_each_crtc(crtc, encoder->dev) { + /* + * reset adj_mode to the mode value each time, + * so we don't adjust the mode twice + */ + drm_mode_copy(&adj_mode, mode); + + crtc_funcs = crtc->helper_private; + if (crtc_funcs && crtc_funcs->mode_fixup) + if (!crtc_funcs->mode_fixup(crtc, mode, &adj_mode)) + return MODE_BAD; + + ret = dsi_encoder_phy_mode_valid(encoder, &adj_mode); + if (ret != MODE_OK) + return ret; + } + return MODE_OK; +} + static void dsi_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) @@ -622,6 +688,7 @@ static int dsi_encoder_atomic_check(struct drm_encoder *encoder, static const struct drm_encoder_helper_funcs dw_encoder_helper_funcs = { .atomic_check = dsi_encoder_atomic_check, + .mode_valid = dsi_encoder_mode_valid, .mode_set = dsi_encoder_mode_set, .enable = dsi_encoder_enable, .disable = dsi_encoder_disable diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index 074b0af..a809ebd 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -178,6 +178,19 @@ static void ade_init(struct ade_hw_ctx *ctx) FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND); } +static bool ade_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct ade_crtc *acrtc = to_ade_crtc(crtc); + struct ade_hw_ctx *ctx = acrtc->ctx; + + adjusted_mode->clock = + clk_round_rate(ctx->ade_pix_clk, mode->clock * 1000) / 1000; + return true; +} + + static void ade_set_pix_clk(struct ade_hw_ctx *ctx, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) @@ -558,6 +571,7 @@ static void ade_crtc_atomic_flush(struct drm_crtc *crtc, static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = { .enable = ade_crtc_enable, .disable = ade_crtc_disable, + .mode_fixup = ade_crtc_mode_fixup, .mode_set_nofb = ade_crtc_mode_set_nofb, .atomic_begin = ade_crtc_atomic_begin, .atomic_flush = ade_crtc_atomic_flush,