From patchwork Thu Jun 22 13:37:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 106216 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp124165qgd; Thu, 22 Jun 2017 06:39:01 -0700 (PDT) X-Received: by 10.98.198.201 with SMTP id x70mr2717074pfk.232.1498138741072; Thu, 22 Jun 2017 06:39:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498138741; cv=none; d=google.com; s=arc-20160816; b=w0wXCgq7PCAGin9n/EwauaqSBHAfTJ6bTIBFHEZ8PR7fbFkkLKDBouDqMUmeaVvGOZ yODt9FqfWa3k9aLEjZ930PVNFhkkF5l/L42jhfrW0TR3z0kRAKnMFr3TPYIJ6hPJ0FqK HThq+fLQS4Fm8551PxAz0XK1krkanLYR7gIlEreX+T+fQZpJ1P01IPIwCT1kOKSD14z7 LVTLnNucgK2TaTB5tQAMk4ruE84gSptjbWM3QVcqWfZ5983VULsw0t8bOHQc1ETQdJIJ eQN8wypvdMraj6bwaDpimnL/RfKbStb9JJcdI3+pZkZSCl1SyFkh/oHukeyPNyDLj3CE cyJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=weUBEwImA9mdEoJ2xIlZpaqYFZExvD7srOJq5XpmU0Q=; b=qtZiz7D8wtXtkvoQap+xM2SvxlEBmoFhLcEOe76gmjOzMYev9uKR0/IYt4/GoCdj6u dgCkaBWt0yvl5cb/2ixyNLykiqnpL0w6I53RHBF3Ah5m5ufnEXOm/W51X1f77iKQvx2v MVL010sbpPY/NJCvZyghDTmxJoPtgVi2QJzOnkpfv1syNEMX5WaZUPUedDpqxWIsuNyH IKRwf09lLmTKpbivQw4lXo9UQP8jyfnqea8QB4CqhuzwZO14K18zbHtfgoBdpKsh7AKT HyOjonvvXzoKJylQNi+4exXKZ/JGdmQfc77QbIb2AM2XDHm7fqDfVvGEFqsgvyFwf1O8 vvoQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y29si1179988pfd.94.2017.06.22.06.39.00; Thu, 22 Jun 2017 06:39:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753556AbdFVNh4 (ORCPT + 25 others); Thu, 22 Jun 2017 09:37:56 -0400 Received: from foss.arm.com ([217.140.101.70]:38380 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753519AbdFVNhw (ORCPT ); Thu, 22 Jun 2017 09:37:52 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8B0E215AD; Thu, 22 Jun 2017 06:37:52 -0700 (PDT) Received: from gby.kfn.arm.com (unknown [10.45.48.178]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C72413F3E1; Thu, 22 Jun 2017 06:37:50 -0700 (PDT) From: Gilad Ben-Yossef To: Greg Kroah-Hartman , linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org Cc: Ofir Drang , Dan Carpenter Subject: [PATCH v2 6/7] staging: ccree: add DT bus coherency detection Date: Thu, 22 Jun 2017 16:37:00 +0300 Message-Id: <1498138623-6126-7-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1498138623-6126-1-git-send-email-gilad@benyossef.com> References: <1498138623-6126-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ccree driver has build time configurable support to work on top of coherent (e.g. ACP) vs. none coherent bus connections. Turn it to run-time configurable option based on device tree. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_buffer_mgr.c | 37 ++++++++++++++++++---------------- drivers/staging/ccree/ssi_config.h | 20 ------------------ drivers/staging/ccree/ssi_driver.c | 12 ++++++++--- drivers/staging/ccree/ssi_driver.h | 3 +++ 4 files changed, 32 insertions(+), 40 deletions(-) -- 2.1.4 diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c index 88ebda8..4373d1d 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.c +++ b/drivers/staging/ccree/ssi_buffer_mgr.c @@ -627,6 +627,7 @@ void ssi_buffer_mgr_unmap_aead_request( struct aead_req_ctx *areq_ctx = aead_request_ctx(req); unsigned int hw_iv_size = areq_ctx->hw_iv_size; struct crypto_aead *tfm = crypto_aead_reqtfm(req); + struct ssi_drvdata *drvdata = dev_get_drvdata(dev); u32 dummy; bool chained; u32 size_to_unmap = 0; @@ -700,8 +701,8 @@ void ssi_buffer_mgr_unmap_aead_request( dma_unmap_sg(dev, req->dst, ssi_buffer_mgr_get_sgl_nents(req->dst,size_to_unmap,&dummy,&chained), DMA_BIDIRECTIONAL); } -#if DX_HAS_ACP - if ((areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) && + if (drvdata->coherent && + (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) && likely(req->src == req->dst)) { u32 size_to_skip = req->assoclen; @@ -716,7 +717,6 @@ void ssi_buffer_mgr_unmap_aead_request( size_to_skip+ req->cryptlen - areq_ctx->req_authsize, size_to_skip+ req->cryptlen, SSI_SG_FROM_BUF); } -#endif } static inline int ssi_buffer_mgr_get_aead_icv_nents( @@ -981,20 +981,24 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( * MAC verification upon request completion */ if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) { -#if !DX_HAS_ACP - /* In ACP platform we already copying ICV - * for any INPLACE-DECRYPT operation, hence + if (!drvdata->coherent) { + /* In coherent platforms (e.g. ACP) + * already copying ICV for any + * INPLACE-DECRYPT operation, hence * we must neglect this code. */ - u32 size_to_skip = req->assoclen; - if (areq_ctx->is_gcm4543) { - size_to_skip += crypto_aead_ivsize(tfm); + u32 skip = req->assoclen; + + if (areq_ctx->is_gcm4543) + skip += crypto_aead_ivsize(tfm); + + ssi_buffer_mgr_copy_scatterlist_portion( + areq_ctx->backup_mac, req->src, + (skip + req->cryptlen - + areq_ctx->req_authsize), + skip + req->cryptlen, + SSI_SG_TO_BUF); } - ssi_buffer_mgr_copy_scatterlist_portion( - areq_ctx->backup_mac, req->src, - size_to_skip+ req->cryptlen - areq_ctx->req_authsize, - size_to_skip+ req->cryptlen, SSI_SG_TO_BUF); -#endif areq_ctx->icv_virt_addr = areq_ctx->backup_mac; } else { areq_ctx->icv_virt_addr = areq_ctx->mac_buf; @@ -1281,8 +1285,8 @@ int ssi_buffer_mgr_map_aead_request( mlli_params->curr_pool = NULL; sg_data.num_of_buffers = 0; -#if DX_HAS_ACP - if ((areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) && + if (drvdata->coherent && + (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) && likely(req->src == req->dst)) { u32 size_to_skip = req->assoclen; @@ -1297,7 +1301,6 @@ int ssi_buffer_mgr_map_aead_request( size_to_skip+ req->cryptlen - areq_ctx->req_authsize, size_to_skip+ req->cryptlen, SSI_SG_TO_BUF); } -#endif /* cacluate the size for cipher remove ICV in decrypt*/ areq_ctx->cryptlen = (areq_ctx->gen_ctx.op_type == diff --git a/drivers/staging/ccree/ssi_config.h b/drivers/staging/ccree/ssi_config.h index 2484a06..ff7597c 100644 --- a/drivers/staging/ccree/ssi_config.h +++ b/drivers/staging/ccree/ssi_config.h @@ -23,7 +23,6 @@ #include -//#define DISABLE_COHERENT_DMA_OPS //#define FLUSH_CACHE_ALL //#define COMPLETION_DELAY //#define DX_DUMP_DESCS @@ -33,24 +32,5 @@ //#define DX_IRQ_DELAY 100000 #define DMA_BIT_MASK_LEN 48 /* was 32 bit, but for juno's sake it was enlarged to 48 bit */ -#if defined (CONFIG_ARM64) // TODO currently only this mode was test on Juno (which is ARM64), need to enable coherent also. -#define DISABLE_COHERENT_DMA_OPS -#endif - -/* Define the CryptoCell DMA cache coherency signals configuration */ -#if defined (DISABLE_COHERENT_DMA_OPS) - /* Software Controlled Cache Coherency (SCCC) */ - #define SSI_CACHE_PARAMS (0x000) - /* CC attached to NONE-ACP such as HPP/ACE/AMBA4. - * The customer is responsible to enable/disable this feature - * according to his platform type. - */ - #define DX_HAS_ACP 0 -#else - #define SSI_CACHE_PARAMS (0xEEE) - /* CC attached to ACP */ - #define DX_HAS_ACP 1 -#endif - #endif /*__DX_CONFIG_H__*/ diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c index 2e251a4..a606ab4 100644 --- a/drivers/staging/ccree/ssi_driver.c +++ b/drivers/staging/ccree/ssi_driver.c @@ -58,6 +58,7 @@ #include #include #include +#include #include "ssi_config.h" #include "ssi_driver.h" @@ -199,7 +200,7 @@ static irqreturn_t cc_isr(int irq, void *dev_id) int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe) { - unsigned int val; + unsigned int val, cache_params; void __iomem *cc_base = drvdata->cc_base; /* Unmask all AXI interrupt sources AXI_CFG1 register */ @@ -232,14 +233,18 @@ int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe) } #endif + cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0); + val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS)); if (is_probe == true) { SSI_LOG_INFO("Cache params previous: 0x%08X\n", val); } - CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS), SSI_CACHE_PARAMS); + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS), + cache_params); val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS)); if (is_probe == true) { - SSI_LOG_INFO("Cache params current: 0x%08X (expected: 0x%08X)\n", val, SSI_CACHE_PARAMS); + SSI_LOG_INFO("Cache params current: 0x%08X (expect: 0x%08X)\n", + val, cache_params); } return 0; @@ -271,6 +276,7 @@ static int init_cc_resources(struct platform_device *plat_dev) new_drvdata->hw_rev_name = hw_rev->name; new_drvdata->hw_rev = hw_rev->rev; new_drvdata->clk = of_clk_get(np, 0); + new_drvdata->coherent = of_dma_is_coherent(np); if (hw_rev->rev >= CC_HW_REV_712) { new_drvdata->hash_len_sz = HASH_LEN_SIZE_712; diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h index a9333892..bdbf1c7 100644 --- a/drivers/staging/ccree/ssi_driver.h +++ b/drivers/staging/ccree/ssi_driver.h @@ -59,6 +59,8 @@ enum cc_hw_rev { CC_HW_REV_712 = 712 }; +#define CC_COHERENT_CACHE_PARAMS 0xEEE + #define SSI_CC_HAS_AES_CCM 1 #define SSI_CC_HAS_AES_GCM 1 #define SSI_CC_HAS_AES_XTS 1 @@ -158,6 +160,7 @@ struct ssi_drvdata { u32 hash_len_sz; u32 axim_mon_offset; struct clk *clk; + bool coherent; }; struct ssi_crypto_alg {