From patchwork Thu Jun 22 12:15:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 106203 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp83646qgd; Thu, 22 Jun 2017 05:16:35 -0700 (PDT) X-Received: by 10.84.224.207 with SMTP id k15mr2612426pln.15.1498133795691; Thu, 22 Jun 2017 05:16:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498133795; cv=none; d=google.com; s=arc-20160816; b=TIZu9q8Zu2k5O/B57Clws3C8WwQlUhkDuIMT+cHFqne6ejbbnaruvV0EWl3GEX+R4N KGnlHeBUQarRyaZpe7p3Uo0EneCRzJlnRDI0K0YYlE7hIFETHbCK4OmTZnhj95rWb1Dg hIpkzicamBx++XCGzGwKbtSmGOXZLuVoNMG1dqKcyEq0b6UX2nsXDKcM9VlrBLCkfFdK bY9owlzu4t754TYksfe1HLgdrHjB5ZOOpQ43W4BlhJHUI2eclJPHxML25dqY0BFTARF/ cv0MA4kVY0EO0uL8pN0mVG2Z+SP8pa3XDdMB89anFcNRD23QitIhlXHh31gzk/rmB28B qxtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=3hEFr3fTvX/Gf17m88pQ3cHmaFAD+KbppIoX/NFZBUk=; b=XgTxnLtxGyYILfPYgr+9MPUF/1uIwEegubrlonNSrERqiwhai5tYLC+WB86OkBX1+z vIL3S9qzFO054SybxuxXQ8ze+F2izFyPYwyu0tvlncFc5oOxzGvsFgc7LcbX0tQZsKn9 UkKDWVj5sf8oOns1Q8+e7EtMUzpXgXzonXIfSpHq7hBF2UXcwc2XDQmL3K0S5/ge/uZv hjoN+JHAr5p+dB19cUwt8FgcUrnN4ZoIq+kDD5JT3pQsq1iR8S01CiSC9w3R7t2W030E DXWvoMRCiPdeSfispXWU8CAvnYkyFTIwfc6QkCfiGwfG76P7KBpCQwF9922Cq+UCu1ye CxKg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g3si1062430pgu.85.2017.06.22.05.16.34; Thu, 22 Jun 2017 05:16:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753246AbdFVMQM (ORCPT + 25 others); Thu, 22 Jun 2017 08:16:12 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:8815 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751893AbdFVMQJ (ORCPT ); Thu, 22 Jun 2017 08:16:09 -0400 Received: from 172.30.72.54 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.54]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APV26033; Thu, 22 Jun 2017 20:15:39 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Thu, 22 Jun 2017 20:15:26 +0800 From: Ding Tianhong To: , , , , , , , , , , , , , , , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v6 1/3] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING Date: Thu, 22 Jun 2017 20:15:19 +0800 Message-ID: <1498133721-21152-2-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1498133721-21152-1-git-send-email-dingtianhong@huawei.com> References: <1498133721-21152-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0205.594BB4EE.0096, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f05a93592527ccb9b35125b1472050d2 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Casey Leedom The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed Ordering Attribute should not be used on Transaction Layer Packets destined for the PCIe End Node so flagged. Initially flagged this way are Intel E5-26xx Root Complex Ports which suffer from a Flow Control Credit Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which don't obey PCIe 3.0 ordering rules which can lead to Data Corruption. Signed-off-by: Casey Leedom Signed-off-by: Ding Tianhong --- drivers/pci/quirks.c | 38 ++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 2 ++ 2 files changed, 40 insertions(+) -- 1.9.0 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 085fb78..58bdd23 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3999,6 +3999,44 @@ static void quirk_tw686x_class(struct pci_dev *pdev) quirk_tw686x_class); /* + * Some devices have problems with Transaction Layer Packets with the Relaxed + * Ordering Attribute set. Such devices should mark themselves and other + * Device Drivers should check before sending TLPs with RO set. + */ +static void quirk_relaxedordering_disable(struct pci_dev *dev) +{ + dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; +} + +/* + * Intel E5-26xx Root Complex has a Flow Control Credit issue which can + * cause performance problems with Upstream Transaction Layer Packets with + * Relaxed Ordering set. + */ +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); + +/* + * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex + * where Upstream Transaction Layer Packets with the Relaxed Ordering + * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering + * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules + * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 + * November 10, 2010). As a result, on this platform we can't use Relaxed + * Ordering for Upstream TLPs. + */ +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); + +/* * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same * values for the Attribute as were supplied in the header of the * corresponding Request, except as explicitly allowed when IDO is used." diff --git a/include/linux/pci.h b/include/linux/pci.h index 8039f9f..ce77690 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -188,6 +188,8 @@ enum pci_dev_flags { * the direct_complete optimization. */ PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11), + /* Don't use Relaxed Ordering for TLPs directed at this device */ + PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12), }; enum pci_irq_reroute_variant {