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[209.132.180.67]) by mx.google.com with ESMTP id a9si14300399pli.135.2017.06.21.02.24.41; Wed, 21 Jun 2017 02:24:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752960AbdFUJYX (ORCPT + 25 others); Wed, 21 Jun 2017 05:24:23 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:8369 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752668AbdFUJYS (ORCPT ); Wed, 21 Jun 2017 05:24:18 -0400 Received: from 172.30.72.53 (EHLO DGGEML401-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APT48847; Wed, 21 Jun 2017 17:23:11 +0800 (CST) Received: from wind-Tecal-RH2285.huawei.com (10.67.212.71) by DGGEML401-HUB.china.huawei.com (10.3.17.32) with Microsoft SMTP Server id 14.3.301.0; Wed, 21 Jun 2017 17:23:02 +0800 From: Jiancheng Xue To: , , , , , CC: , , , , , , , Jiancheng Xue Subject: [PATCH 4/5] arm64: dts: hisilicon: add usb2 controller and phy nodes for poplar board. Date: Wed, 21 Jun 2017 17:00:44 +0800 Message-ID: <1498035645-22804-5-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> References: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.71] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.594A3B00.0040, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a1b927784408f8bdcf589bb9b6dd1127 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add usb2 controller and phy nodes for poplar board. Signed-off-by: Jiancheng Xue Reviewed-by: Daniel Thompson --- .../boot/dts/hisilicon/hi3798cv200-poplar.dts | 13 ++++++ arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 47 ++++++++++++++++++++++ 2 files changed, 60 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts index 684fa09..40db803 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts @@ -64,6 +64,10 @@ }; }; +&ehci { + status = "okay"; +}; + &gmac1 { status = "okay"; #address-cells = <1>; @@ -147,6 +151,10 @@ status = "okay"; }; +&ohci { + status = "okay"; +}; + &spi0 { status = "okay"; label = "LS-SPI0"; @@ -161,3 +169,8 @@ label = "LS-UART0"; }; /* No optional LS-UART1 on Low Speed Expansion Connector. */ + +&usb2_phy1 { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 75865f8a..422aeaf 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -106,6 +106,11 @@ #reset-cells = <2>; }; + peri_ctrl: system-controller@8a20000 { + compatible = "syscon"; + reg = <0x8a20000 0x1000>; + }; + uart0: serial@8b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; @@ -407,5 +412,47 @@ clocks = <&sysctrl HISTB_IR_CLK>; status = "disabled"; }; + + ehci: ehci@0x9890000 { + compatible = "generic-ehci"; + reg = <0x9890000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_PHY_CLK>; + clock-names = "ehci_system", "phy"; + resets = <&crg 0xb8 12>, + <&crg 0xb8 16>; + reset-names = "bus", "phy"; + status = "disabled"; + }; + + ohci: ohci@0x9880000 { + compatible = "generic-ohci"; + reg = <0x9880000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_12M_CLK>, + <&crg HISTB_USB2_48M_CLK>; + clock-names = "ahb_biu", "clk12", "clk48"; + resets = <&crg 0xb8 12>; + reset-names = "bus"; + status = "disabled"; + }; + + usb2_phy1: usb-phy@1 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + #phy-cells = <0>; + hisilicon,peripheral-syscon = <&peri_ctrl>; + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; + resets = <&crg 0xbc 4>; + reset-names = "por_rst"; + status = "disabled"; + + usb2_port1: port@1 { + clocks = <&crg HISTB_USB2_UTMI_CLK>; + resets = <&crg 0xbc 9>, <&crg 0xb8 13>; + reset-names = "port_rst", "utmi_rst"; + }; + }; }; };