From patchwork Tue Jun 20 15:06:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 106007 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp1421732qgd; Tue, 20 Jun 2017 08:07:32 -0700 (PDT) X-Received: by 10.84.232.135 with SMTP id i7mr9211932plk.300.1497971252517; Tue, 20 Jun 2017 08:07:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497971252; cv=none; d=google.com; s=arc-20160816; b=zdb1aHyTojyLObMx7ToophRZOb95MYOr2+ActN6Bot9bOWHgC0ZqSFR/SrMlFZlpGa soanpXRHP5u0hF3c+uov5Lq1KT2QqFZDygIgUYSMoUI/6L4tYWNjFU4AceztfylGcXNZ zqn0ShLFai2eaMDpZrf7IXY8gmdt4H2S60vMhJjPWEXvZTI7JlKck9inQDqDUwHaScmC COQxMvG2katkbvpZyjlCA852/xDdSBADGJ04PqBAALCVamZDy79XsW12ygXT9zEKMnWL xN4cvU2GEy/8vIgTFUUYH84t7ekFKCVvFLQt7xKMKb3vgORtSunKORHKOjJjh8AvRF3V KbXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter:arc-authentication-results; bh=A4VTCSG4astt06M4wTlvIRJD8aiMBftQwb2QLMTkyBw=; b=R3ehxzM7rqnud9WrnBtQF6WIjdSt/mBoMcdeGyxc0rMc51zZrja7AniPy+JIaTXoEK LyWmbbsRKiWLHpXtXDeuhwEwetzdS/AW3181JUhy93aeMFrDNwBzubbnZUmT/1VDxUBf uYwNJGDYEUNXqC/NhVRRF6HoTzP2jeCLQDkRH15ZO7zinxF+JBBZGQRd9CNew18+akZ8 aRXl9QxuJejW5WBqTojW7tfpSIZeeNWX6f6b+5ORp+8xEDP9psptL2jYd01BTAdXE2w3 JgrAWncozSDnRKH8M/dQeA3FejMriZlcbfkmLu/aO5M52y/H3L2ss6JdnKIviFucEUki CpvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.b=RDZFwZBh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k7si6845006pgf.209.2017.06.20.08.07.32; Tue, 20 Jun 2017 08:07:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.b=RDZFwZBh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751883AbdFTPHY (ORCPT + 25 others); Tue, 20 Jun 2017 11:07:24 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:61462 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751120AbdFTPHX (ORCPT ); Tue, 20 Jun 2017 11:07:23 -0400 Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-07.nifty.com with ESMTP id v5KF6Inw016495; Wed, 21 Jun 2017 00:06:22 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v5KF6Inw016495 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1497971182; bh=A4VTCSG4astt06M4wTlvIRJD8aiMBftQwb2QLMTkyBw=; h=From:To:Cc:Subject:Date:From; b=RDZFwZBh9SU954+4v9SuyofbjQH4Fsrsi2eQ/jsBHCJCABfwqveGhhOcILGq7iglN g5Z6Pj5ymj6caSwC3aEpzuEbv8APA6PiD2oNSEOmqkhrABe/2sqHzhSx2nfOh1J7kU xrc4uSfrRFJSONFZm5vdexbLeNpK21vNt6GMmRbKoucF2TUP+xppbkX3j0Joe/ZLdH LdR7/DckiqaUBUh2YbEQ3khos1kdsVyNIE21bfPH2GiEcZhJyYFSBck7nF+qGwgJEa 7EhFjlDClv9EYifk2hQ7yO77w23OCXVphHfND63xK/2mkcDosVZ5dOlKTZw4cjppxv SvK+q1JUpAJyQ== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: linux-clk@vger.kernel.org Cc: Masahiro Yamada , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH] clk: uniphier: provide NAND controller clock rate Date: Wed, 21 Jun 2017 00:06:03 +0900 Message-Id: <1497971163-9206-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This allows the NAND driver to get the clock rate via clk_get_rate(). Signed-off-by: Masahiro Yamada --- drivers/clk/uniphier/clk-uniphier-sys.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index c8027d9..ad02181 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -29,11 +29,18 @@ UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \ UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15) +/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */ #define UNIPHIER_SLD3_SYS_CLK_NAND(idx) \ - UNIPHIER_CLK_GATE("nand", (idx), NULL, 0x2104, 2) + UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 8), \ + UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2) + +#define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \ + UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 12), \ + UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2) #define UNIPHIER_LD11_SYS_CLK_NAND(idx) \ - UNIPHIER_CLK_GATE("nand", (idx), NULL, 0x210c, 0) + UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 10), \ + UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x210c, 0) #define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \ UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2) @@ -114,7 +121,7 @@ const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), - UNIPHIER_SLD3_SYS_CLK_NAND(2), + UNIPHIER_PRO5_SYS_CLK_NAND(2), UNIPHIER_PRO5_SYS_CLK_SD, UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC */ UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */ @@ -127,7 +134,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), - UNIPHIER_SLD3_SYS_CLK_NAND(2), + UNIPHIER_PRO5_SYS_CLK_NAND(2), UNIPHIER_PRO5_SYS_CLK_SD, UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, RLE */ /* GIO is always clock-enabled: no function for 0x2104 bit6 */