From patchwork Mon Jun 19 18:32:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Willy Tarreau X-Patchwork-Id: 105922 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp1030893qgd; Mon, 19 Jun 2017 12:32:35 -0700 (PDT) X-Received: by 10.101.83.197 with SMTP id z5mr18251277pgr.256.1497900754835; Mon, 19 Jun 2017 12:32:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497900754; cv=none; d=google.com; s=arc-20160816; b=IEMRcshZC7c4CwtXOkFUR1Y993cDfei0Cu+G92sQSLcAbe7ZBXOyQBrJ87Skub2Vua GlRrnacd6oC4P8++lqIdWF1ecoKNr75OuJ/RmORZxRxumqtlpwulQyzSfZDoILPCAoa4 ud7LQ0oguU7hmlUpe6myh1/2oaMUnbmai5b4qKNrMj+rP9JAFYUeSS/66EgBV4ul/TH0 pgtrR2DVm076HF3tTQAcZc+xGhcpisklaXZr12Tmo9LWKAeRNltR8hCibcMc1uN8QOV/ alyFbV2jnNH/UWB7NpruXdss4Lv63WsfREEtMUNhVn9UdTRtIuKFakDl8jmWLPuBuAjd xpOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=qnxAqwcEEW79+o92E1RIILmg6OgVwhVMhibRtyjhpuQ=; b=GDkHlydFS7BK5JeVAkJoY3PpImUs89lBIrSqKGo0THLpkkVXdDi4y7i6YW9yXlZDGU Ygorbk5Ik3UjPJECm9hqbsBglKXuz6OLVbVSL2mAGQg558GwQOj2atYsh5sT4cYC/qj3 8GUnHqcAnweY930UH0EAUbL++Na2AzXd8Fk9GNl0KwIFrSxTgy3f+Xc4TprZ96MImI+y 7fvaVQYIUW9YeB+71MwUTpJTKm0823Cl3WxHDAsHrg7DgFR7hmGdJHR5XEg+YJvcj0yj 2HF8icCu5mEynSu7Xby1zM8z9G9ESI3Xn7L1cI0knyS1iRS90mHwb9ugxE37Tv9RKyDR 3D+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l91si9948707plb.581.2017.06.19.12.32.34; Mon, 19 Jun 2017 12:32:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752919AbdFSTcR (ORCPT + 25 others); Mon, 19 Jun 2017 15:32:17 -0400 Received: from wtarreau.pck.nerim.net ([62.212.114.60]:51973 "EHLO 1wt.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752710AbdFSSey (ORCPT ); Mon, 19 Jun 2017 14:34:54 -0400 Received: (from willy@localhost) by pcw.home.local (8.15.2/8.15.2/Submit) id v5JIY2tJ015122; Mon, 19 Jun 2017 20:34:02 +0200 From: Willy Tarreau To: linux-kernel@vger.kernel.org, stable@vger.kernel.org, linux@roeck-us.net Cc: Corey Minyard , David Daney , linux-mips@linux-mips.org, Ralf Baechle , Julia Lawall , Jiri Slaby , Willy Tarreau Subject: [PATCH 3.10 256/268] MIPS: Fix crash registers on non-crashing CPUs Date: Mon, 19 Jun 2017 20:32:35 +0200 Message-Id: <1497897167-14556-257-git-send-email-w@1wt.eu> X-Mailer: git-send-email 2.8.0.rc2.1.gbe9624a In-Reply-To: <1497897167-14556-1-git-send-email-w@1wt.eu> References: <1497897167-14556-1-git-send-email-w@1wt.eu> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Corey Minyard commit c80e1b62ffca52e2d1d865ee58bc79c4c0c55005 upstream. As part of handling a crash on an SMP system, an IPI is send to all other CPUs to save their current registers and stop. It was using task_pt_regs(current) to get the registers, but that will only be accurate if the CPU was interrupted running in userland. Instead allow the architecture to pass in the registers (all pass NULL now, but allow for the future) and then use get_irq_regs() which should be accurate as we are in an interrupt. Fall back to task_pt_regs(current) if nothing else is available. Signed-off-by: Corey Minyard Cc: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13050/ Signed-off-by: Ralf Baechle Cc: Julia Lawall Signed-off-by: Jiri Slaby Signed-off-by: Willy Tarreau --- arch/mips/kernel/crash.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) -- 2.8.0.rc2.1.gbe9624a diff --git a/arch/mips/kernel/crash.c b/arch/mips/kernel/crash.c index 93aa302..c683129 100644 --- a/arch/mips/kernel/crash.c +++ b/arch/mips/kernel/crash.c @@ -15,12 +15,22 @@ static int crashing_cpu = -1; static cpumask_t cpus_in_crash = CPU_MASK_NONE; #ifdef CONFIG_SMP -static void crash_shutdown_secondary(void *ignore) +static void crash_shutdown_secondary(void *passed_regs) { - struct pt_regs *regs; + struct pt_regs *regs = passed_regs; int cpu = smp_processor_id(); - regs = task_pt_regs(current); + /* + * If we are passed registers, use those. Otherwise get the + * regs from the last interrupt, which should be correct, as + * we are in an interrupt. But if the regs are not there, + * pull them from the top of the stack. They are probably + * wrong, but we need something to keep from crashing again. + */ + if (!regs) + regs = get_irq_regs(); + if (!regs) + regs = task_pt_regs(current); if (!cpu_online(cpu)) return;