From patchwork Wed Jun 14 12:39:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105513 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp273102qgd; Wed, 14 Jun 2017 05:45:20 -0700 (PDT) X-Received: by 10.98.36.135 with SMTP id k7mr443374pfk.62.1497444320511; Wed, 14 Jun 2017 05:45:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444320; cv=none; d=google.com; s=arc-20160816; b=V9ru4y5XNySeLE/o5G3PIqC9gXaVr4V4KgH8QGjykYvistC2StIyOmJqskVQWR1Qu7 Asof1jHjMc6lwO/DrHLCN63pRu5u3mDVI4+vdZ2R5yIKLwNDMxtenV5UFzg/OKlFIr9k 5kWatktwpn9gG/QOAdGMoNgdvPRtDefSIHfZNVDqgpRVXiRSPUadrQAVF1F+3rhl779O ADVKNV+VwRW/2PyRfWO2YfVKdFobbhRdSFlRWSP4seX+XNEJds0tuQHtsGotMiIA0Wt8 oYSrN5JcXMTI/1S49YgH2A5mKRbegPB2EFeFHn8rM/pRYmLCkyFT869cuqo8AKbfZqHO oNQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=qoIdSuizDl/eUbdd32DNfabFLp2i25L6mzzJrzAyNJw=; b=cVNqF6mIfAxTUp45oXOv52V4tHbz73SbHoo5TqI4IWLvm3R+4Q1H/a3HlAxTX1Gqh7 1Os0Dfoqu1D0hpswhMA9u4LEY2P51fI8Pg2//Px4D5TcfJa/r/HDcwby/nacdm1JTimW RMWkVn1qHiMWXEslrsABVJFIm3EmTvokrIWEl5xpml6lhVLKc/kKGTu+m4tpS7JniPnQ M5YKMBo+dwrz8+wYbP4dp+hmrJcMKPKRHRzyBDS7kYjdYv7aP0CmG2YcQwLfLhdVQ4wO 2Ru5xDdH8UuoGkPYG6uyHmHuskUpWtNFvYgJUWR4lk3h72sEmFPx71tUPc3vFGlshgbZ gnww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=HjFWDoAo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a7si651899plt.37.2017.06.14.05.45.20; Wed, 14 Jun 2017 05:45:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=HjFWDoAo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752710AbdFNMpS (ORCPT + 25 others); Wed, 14 Jun 2017 08:45:18 -0400 Received: from mail-wr0-f175.google.com ([209.85.128.175]:36229 "EHLO mail-wr0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752519AbdFNMlJ (ORCPT ); Wed, 14 Jun 2017 08:41:09 -0400 Received: by mail-wr0-f175.google.com with SMTP id 36so66270377wry.3 for ; Wed, 14 Jun 2017 05:41:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qoIdSuizDl/eUbdd32DNfabFLp2i25L6mzzJrzAyNJw=; b=HjFWDoAocLzTjTe1hfLqlaLBeF9jXRhjyNomrTCTqtPXGmdL/ulVYb8oRRPYw9DwSW BdMg5GL0XIWceI/n0+BpeXDIRpWsNxrmGyFmSDk1e3+Nk7V5834JE2gJNza9U/SGiFBE +1rbhMOQY1chOi5F60VTScFxKWqRwqUIyg2JA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qoIdSuizDl/eUbdd32DNfabFLp2i25L6mzzJrzAyNJw=; b=AgWKgA9HaWB/h9ZfOmEjZpaUOJfOpqnBZMXlOi3n7Fo/o2VWEEiRUtd2M+W9LaVs3z A8mebgKTsDgp2P29P2FbefwnCV8zj1S9PDN99NDofNGfCMnzWFtC8DMU5bbsyhghA4mz RztE0Gl+h4CdNREQw/Flbn1+vGMgcWAejbFtqnWwahxJLOmzlodtSEhCS+TJEcgHgL0u KGt2HsHAPfmFI/IM8TEITwG3fv9WwcECrpUOCxUC0whBRDfkO2Keccf900n8PkpwHj9h TbYpYDb3OEQSqypLD2YECCfxoGB7g+sU2jFLBedVl4rXdgvi+HxOXyU424Cy6UaeC9A5 Vxbg== X-Gm-Message-State: AKS2vOxri4oIx/5CkkffPLuPKvbTKzkcw2K8RrFkJIE1kdiiSAG8ctAQ 4yw5hisOyOpnddN2 X-Received: by 10.28.130.196 with SMTP id e187mr985005wmd.24.1497444063183; Wed, 14 Jun 2017 05:41:03 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.41.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:41:02 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Joel Stanley , Jonas Jensen Subject: [PATCH 06/23] clocksource/drivers/fttmr010: Switch to use bitops Date: Wed, 14 Jun 2017 14:39:27 +0200 Message-Id: <1497443984-12371-6-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij This switches the drivers to use the bitops BIT() macro to define bits. Cc: Joel Stanley Tested-by: Jonas Jensen Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 43 ++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 21 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index 9ad3148..9df14cf 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -16,6 +16,7 @@ #include #include #include +#include /* * Register definitions for the timers @@ -36,31 +37,31 @@ #define TIMER_INTR_STATE (0x34) #define TIMER_INTR_MASK (0x38) -#define TIMER_1_CR_ENABLE (1 << 0) -#define TIMER_1_CR_CLOCK (1 << 1) -#define TIMER_1_CR_INT (1 << 2) -#define TIMER_2_CR_ENABLE (1 << 3) -#define TIMER_2_CR_CLOCK (1 << 4) -#define TIMER_2_CR_INT (1 << 5) -#define TIMER_3_CR_ENABLE (1 << 6) -#define TIMER_3_CR_CLOCK (1 << 7) -#define TIMER_3_CR_INT (1 << 8) -#define TIMER_1_CR_UPDOWN (1 << 9) -#define TIMER_2_CR_UPDOWN (1 << 10) -#define TIMER_3_CR_UPDOWN (1 << 11) +#define TIMER_1_CR_ENABLE BIT(0) +#define TIMER_1_CR_CLOCK BIT(1) +#define TIMER_1_CR_INT BIT(2) +#define TIMER_2_CR_ENABLE BIT(3) +#define TIMER_2_CR_CLOCK BIT(4) +#define TIMER_2_CR_INT BIT(5) +#define TIMER_3_CR_ENABLE BIT(6) +#define TIMER_3_CR_CLOCK BIT(7) +#define TIMER_3_CR_INT BIT(8) +#define TIMER_1_CR_UPDOWN BIT(9) +#define TIMER_2_CR_UPDOWN BIT(10) +#define TIMER_3_CR_UPDOWN BIT(11) #define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \ TIMER_3_CR_ENABLE | \ TIMER_3_CR_UPDOWN) -#define TIMER_1_INT_MATCH1 (1 << 0) -#define TIMER_1_INT_MATCH2 (1 << 1) -#define TIMER_1_INT_OVERFLOW (1 << 2) -#define TIMER_2_INT_MATCH1 (1 << 3) -#define TIMER_2_INT_MATCH2 (1 << 4) -#define TIMER_2_INT_OVERFLOW (1 << 5) -#define TIMER_3_INT_MATCH1 (1 << 6) -#define TIMER_3_INT_MATCH2 (1 << 7) -#define TIMER_3_INT_OVERFLOW (1 << 8) +#define TIMER_1_INT_MATCH1 BIT(0) +#define TIMER_1_INT_MATCH2 BIT(1) +#define TIMER_1_INT_OVERFLOW BIT(2) +#define TIMER_2_INT_MATCH1 BIT(3) +#define TIMER_2_INT_MATCH2 BIT(4) +#define TIMER_2_INT_OVERFLOW BIT(5) +#define TIMER_3_INT_MATCH1 BIT(6) +#define TIMER_3_INT_MATCH2 BIT(7) +#define TIMER_3_INT_OVERFLOW BIT(8) #define TIMER_INT_ALL_MASK 0x1ff struct fttmr010 {