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[209.132.180.67]) by mx.google.com with ESMTP id 89si625331plc.277.2017.06.14.05.41.25; Wed, 14 Jun 2017 05:41:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=ULQs028k; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752518AbdFNMlG (ORCPT + 25 others); Wed, 14 Jun 2017 08:41:06 -0400 Received: from mail-wr0-f171.google.com ([209.85.128.171]:35717 "EHLO mail-wr0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752394AbdFNMlD (ORCPT ); Wed, 14 Jun 2017 08:41:03 -0400 Received: by mail-wr0-f171.google.com with SMTP id q97so188223527wrb.2 for ; Wed, 14 Jun 2017 05:41:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cvEfStQjch/lC7vl/dWjDPjvCYU1AknIn1uFt0zQE4E=; b=ULQs028klUgQLy0xFHXG9iYvTYJhPvOAu3twHk4V4KgxRFf1eMpbi4eI2bTE2fTN33 c/0q0/ISWgAYyp5qDhSl9Rd/TZmZvqiNMnDD/++sRftQ5z8RwF7TjaCOlX7QCfg05vL7 Yhxv2P0imlVbHpayyJrYS4VG0rAe7T8CZF4OY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cvEfStQjch/lC7vl/dWjDPjvCYU1AknIn1uFt0zQE4E=; b=VJIxUF3mHQEfDtgLw4+CSN+7Sq6egzc8Ma/qsNAAqDmYeSzh/txUj+R5Atc4Nuo9VR 4m1RJEOhWYOvJ6nbik3QaWReWU/OpWHRbXZyTo//vD6iVIlygE6sou8JT3WLXhyeKQX8 Xo8Qvwge1AZdUBkcTbWhWf6L8XZfYuO9fRDdMBLQhnLVyFbTZAVHKT9TyIHKP7Ww1dOo 0XUEq4Ujn/pBEjdH/6POPWGP+0ILHm/be0UlJLxDdUAMg2akkvEoW9xbYaASDs7iei1x zxq6Wq4xc/pzMA3XzUJpQ9te+X/jkEY4AxVti7Q+SRZuZUbbFwAOvYOr6WQyOSbeM5D+ vHDA== X-Gm-Message-State: AKS2vOwlXwVIub2eymRFxKy9ryM/pU0AzUWG0QvkNbK7PGxPcQso9ZR+ 29qY9GBE05xgA81d X-Received: by 10.28.214.211 with SMTP id n202mr932004wmg.105.1497444061884; Wed, 14 Jun 2017 05:41:01 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.41.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:41:01 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Joel Stanley , Jonas Jensen Subject: [PATCH 05/23] clocksource/drivers/fttmr010: Use state container Date: Wed, 14 Jun 2017 14:39:26 +0200 Message-Id: <1497443984-12371-5-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij This converts the Faraday FTTMR010 to use the state container design pattern. Take some care to handle the state container and free:ing of resources as has been done in the Moxa driver. Cc: Joel Stanley Tested-by: Jonas Jensen Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 190 +++++++++++++++++++++-------------- 1 file changed, 116 insertions(+), 74 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index db097db..9ad3148 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -15,6 +15,7 @@ #include #include #include +#include /* * Register definitions for the timers @@ -62,23 +63,35 @@ #define TIMER_3_INT_OVERFLOW (1 << 8) #define TIMER_INT_ALL_MASK 0x1ff -static unsigned int tick_rate; -static void __iomem *base; +struct fttmr010 { + void __iomem *base; + unsigned int tick_rate; + struct clock_event_device clkevt; +}; + +/* A local singleton used by sched_clock, which is stateless */ +static struct fttmr010 *local_fttmr; + +static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt) +{ + return container_of(evt, struct fttmr010, clkevt); +} static u64 notrace fttmr010_read_sched_clock(void) { - return readl(base + TIMER3_COUNT); + return readl(local_fttmr->base + TIMER3_COUNT); } static int fttmr010_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { + struct fttmr010 *fttmr010 = to_fttmr010(evt); u32 cr; /* Setup the match register */ - cr = readl(base + TIMER1_COUNT); - writel(cr + cycles, base + TIMER1_MATCH1); - if (readl(base + TIMER1_COUNT) - cr > cycles) + cr = readl(fttmr010->base + TIMER1_COUNT); + writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); + if (readl(fttmr010->base + TIMER1_COUNT) - cr > cycles) return -ETIME; return 0; @@ -86,99 +99,90 @@ static int fttmr010_timer_set_next_event(unsigned long cycles, static int fttmr010_timer_shutdown(struct clock_event_device *evt) { + struct fttmr010 *fttmr010 = to_fttmr010(evt); + u32 cr; + + /* Stop timer and interrupt. */ + cr = readl(fttmr010->base + TIMER_CR); + cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); + writel(cr, fttmr010->base + TIMER_CR); + + return 0; +} + +static int fttmr010_timer_set_oneshot(struct clock_event_device *evt) +{ + struct fttmr010 *fttmr010 = to_fttmr010(evt); u32 cr; - /* - * Disable also for oneshot: the set_next() call will arm the timer - * instead. - */ /* Stop timer and interrupt. */ - cr = readl(base + TIMER_CR); + cr = readl(fttmr010->base + TIMER_CR); cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); - writel(cr, base + TIMER_CR); + writel(cr, fttmr010->base + TIMER_CR); /* Setup counter start from 0 */ - writel(0, base + TIMER1_COUNT); - writel(0, base + TIMER1_LOAD); + writel(0, fttmr010->base + TIMER1_COUNT); + writel(0, fttmr010->base + TIMER1_LOAD); - /* enable interrupt */ - cr = readl(base + TIMER_INTR_MASK); + /* Enable interrupt */ + cr = readl(fttmr010->base + TIMER_INTR_MASK); cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); cr |= TIMER_1_INT_MATCH1; - writel(cr, base + TIMER_INTR_MASK); + writel(cr, fttmr010->base + TIMER_INTR_MASK); - /* start the timer */ - cr = readl(base + TIMER_CR); + /* Start the timer */ + cr = readl(fttmr010->base + TIMER_CR); cr |= TIMER_1_CR_ENABLE; - writel(cr, base + TIMER_CR); + writel(cr, fttmr010->base + TIMER_CR); return 0; } static int fttmr010_timer_set_periodic(struct clock_event_device *evt) { - u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ); + struct fttmr010 *fttmr010 = to_fttmr010(evt); + u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ); u32 cr; /* Stop timer and interrupt */ - cr = readl(base + TIMER_CR); + cr = readl(fttmr010->base + TIMER_CR); cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); - writel(cr, base + TIMER_CR); + writel(cr, fttmr010->base + TIMER_CR); /* Setup timer to fire at 1/HT intervals. */ cr = 0xffffffff - (period - 1); - writel(cr, base + TIMER1_COUNT); - writel(cr, base + TIMER1_LOAD); + writel(cr, fttmr010->base + TIMER1_COUNT); + writel(cr, fttmr010->base + TIMER1_LOAD); /* enable interrupt on overflow */ - cr = readl(base + TIMER_INTR_MASK); + cr = readl(fttmr010->base + TIMER_INTR_MASK); cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2); cr |= TIMER_1_INT_OVERFLOW; - writel(cr, base + TIMER_INTR_MASK); + writel(cr, fttmr010->base + TIMER_INTR_MASK); /* Start the timer */ - cr = readl(base + TIMER_CR); + cr = readl(fttmr010->base + TIMER_CR); cr |= TIMER_1_CR_ENABLE; cr |= TIMER_1_CR_INT; - writel(cr, base + TIMER_CR); + writel(cr, fttmr010->base + TIMER_CR); return 0; } -/* Use TIMER1 as clock event */ -static struct clock_event_device fttmr010_clockevent = { - .name = "TIMER1", - /* Reasonably fast and accurate clock event */ - .rating = 300, - .shift = 32, - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = fttmr010_timer_set_next_event, - .set_state_shutdown = fttmr010_timer_shutdown, - .set_state_periodic = fttmr010_timer_set_periodic, - .set_state_oneshot = fttmr010_timer_shutdown, - .tick_resume = fttmr010_timer_shutdown, -}; - /* * IRQ handler for the timer */ static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id) { - struct clock_event_device *evt = &fttmr010_clockevent; + struct clock_event_device *evt = dev_id; evt->event_handler(evt); return IRQ_HANDLED; } -static struct irqaction fttmr010_timer_irq = { - .name = "Faraday FTTMR010 Timer Tick", - .flags = IRQF_TIMER, - .handler = fttmr010_timer_interrupt, -}; - static int __init fttmr010_timer_init(struct device_node *np) { + struct fttmr010 *fttmr010; int irq; struct clk *clk; int ret; @@ -198,53 +202,91 @@ static int __init fttmr010_timer_init(struct device_node *np) pr_err("failed to enable PCLK\n"); return ret; } - tick_rate = clk_get_rate(clk); - base = of_iomap(np, 0); - if (!base) { + fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL); + if (!fttmr010) { + ret = -ENOMEM; + goto out_disable_clock; + } + fttmr010->tick_rate = clk_get_rate(clk); + + fttmr010->base = of_iomap(np, 0); + if (!fttmr010->base) { pr_err("Can't remap registers"); - return -ENXIO; + ret = -ENXIO; + goto out_free; } /* IRQ for timer 1 */ irq = irq_of_parse_and_map(np, 0); if (irq <= 0) { pr_err("Can't parse IRQ"); - return -EINVAL; + ret = -EINVAL; + goto out_unmap; } /* * Reset the interrupt mask and status */ - writel(TIMER_INT_ALL_MASK, base + TIMER_INTR_MASK); - writel(0, base + TIMER_INTR_STATE); - writel(TIMER_DEFAULT_FLAGS, base + TIMER_CR); + writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); + writel(0, fttmr010->base + TIMER_INTR_STATE); + writel(TIMER_DEFAULT_FLAGS, fttmr010->base + TIMER_CR); /* * Setup free-running clocksource timer (interrupts * disabled.) */ - writel(0, base + TIMER3_COUNT); - writel(0, base + TIMER3_LOAD); - writel(0, base + TIMER3_MATCH1); - writel(0, base + TIMER3_MATCH2); - clocksource_mmio_init(base + TIMER3_COUNT, - "fttmr010_clocksource", tick_rate, + local_fttmr = fttmr010; + writel(0, fttmr010->base + TIMER3_COUNT); + writel(0, fttmr010->base + TIMER3_LOAD); + writel(0, fttmr010->base + TIMER3_MATCH1); + writel(0, fttmr010->base + TIMER3_MATCH2); + clocksource_mmio_init(fttmr010->base + TIMER3_COUNT, + "FTTMR010-TIMER3", + fttmr010->tick_rate, 300, 32, clocksource_mmio_readl_up); - sched_clock_register(fttmr010_read_sched_clock, 32, tick_rate); + sched_clock_register(fttmr010_read_sched_clock, 32, + fttmr010->tick_rate); /* - * Setup clockevent timer (interrupt-driven.) + * Setup clockevent timer (interrupt-driven) on timer 1. */ - writel(0, base + TIMER1_COUNT); - writel(0, base + TIMER1_LOAD); - writel(0, base + TIMER1_MATCH1); - writel(0, base + TIMER1_MATCH2); - setup_irq(irq, &fttmr010_timer_irq); - fttmr010_clockevent.cpumask = cpumask_of(0); - clockevents_config_and_register(&fttmr010_clockevent, tick_rate, + writel(0, fttmr010->base + TIMER1_COUNT); + writel(0, fttmr010->base + TIMER1_LOAD); + writel(0, fttmr010->base + TIMER1_MATCH1); + writel(0, fttmr010->base + TIMER1_MATCH2); + ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER, + "FTTMR010-TIMER1", &fttmr010->clkevt); + if (ret) { + pr_err("FTTMR010-TIMER1 no IRQ\n"); + goto out_unmap; + } + + fttmr010->clkevt.name = "FTTMR010-TIMER1"; + /* Reasonably fast and accurate clock event */ + fttmr010->clkevt.rating = 300; + fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT; + fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event; + fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown; + fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic; + fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot; + fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown; + fttmr010->clkevt.cpumask = cpumask_of(0); + fttmr010->clkevt.irq = irq; + clockevents_config_and_register(&fttmr010->clkevt, + fttmr010->tick_rate, 1, 0xffffffff); return 0; + +out_unmap: + iounmap(fttmr010->base); +out_free: + kfree(fttmr010); +out_disable_clock: + clk_disable_unprepare(clk); + + return ret; } CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init); CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);