From patchwork Tue Jun 13 05:04:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 103699 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp236168qgd; Mon, 12 Jun 2017 22:07:43 -0700 (PDT) X-Received: by 10.99.129.66 with SMTP id t63mr33928180pgd.28.1497330462948; Mon, 12 Jun 2017 22:07:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497330462; cv=none; d=google.com; s=arc-20160816; b=LRJhRpOCgVWf2G0LOtaC2KjsbwYKW9sJyFM1ft7S9agyxFZOY5hq90XQfRFB+aWlmC 1iHgBQrS0Eleg1K5GyW6a/SkScE8A7DziNbiy6wkw2iQ7fdRQj63WM3WQ3cheQZjQQy1 DBJkFgy7mwybBd2gHjfwzv9psN3LyQAt9CgArNHs4jcHUy+G+zS7n1VxTljPEDIKmZFq 8id6Gps/hQGmr5dXVYQcUhGTixW4J3zfe04Y83RpzoIZtNRv07wXlekSvHzDk0Q+ESRN PVTKirzNsYzpJFaaM+1ojmzj9MaRzpkIhxQMoaFOWPhHLy5Y0hhPLCsQTEhjKXfXkI0g 5G8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=t//WkJGgtIURlAFYnf14igJX6ojQBKdCoXKQ4jzyvpw=; b=LkOcXS8QORLj+x5MqpPvX3MKpyrMPIVhAe6OeMUzLaj1fBHJ9FDh7sr9JPI3eNkzbB H1Jm7R4xunFtG2uz8vTzhzwAVBGr7ZVaqcTI+vPjA7557rxrcA3gDLvNrBE+SVGTovnX incIngtWa79vklp/ILNsU/Ok7KoOitT+4grzuV+ff7zkmmtR3XsErnVKlpf6l705HQPT 7fQJ4B0J/VoKEzj31F8F24YvESvR8xV+0jQ5+TX8el/3sZmYHVyccSlIEXKKQWEaJcN2 z/l5qKFQFjC2HBz8ntX07oKUG9HBNEz8dbpKrHSSJZJV1noqLP69YAApoqH+eNAkpIe8 LFLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1si8251437plx.88.2017.06.12.22.07.42; Mon, 12 Jun 2017 22:07:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752517AbdFMFHc (ORCPT + 25 others); Tue, 13 Jun 2017 01:07:32 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:47956 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752479AbdFMFH1 (ORCPT ); Tue, 13 Jun 2017 01:07:27 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v5D54ENs023096; Tue, 13 Jun 2017 14:04:31 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v5D54ENs023096 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1497330271; bh=t//WkJGgtIURlAFYnf14igJX6ojQBKdCoXKQ4jzyvpw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wLQKxJOIHztf9S0yzSsuaBkZaHkb8WN2vBVTdul12F0/D+cGNVccXgCGzbuIhWOMt EJ5MoAKfwcD/7JxvOl4Ngk+yeTpjxfw9J0mXqoPeUlwbOQ2GoBWZOSmrtBwlBBnmkP INALJRXKqbHDjfChQyqL98JJ1cCTYcJBKnULirtuiGqixdiivNQ7tw9E5AksJnWNRG dJV7avVIcte6hCb5Q42NEPdpydXOLVQ4RTbDAQh0pWPueuqC+A0/CGVujWBIHicEGA tQqBaxJR9blNVMD/nTJ4pHDMBaAZMJzrWNWbXR3zF5KhtdvjbTHxPG/RQ5PVufLZEi aswkBwrr/SPoA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger Subject: [PATCH v6 14/18] mtd: nand: denali: support hardware-assisted erased page detection Date: Tue, 13 Jun 2017 14:04:06 +0900 Message-Id: <1497330250-17348-15-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497330250-17348-1-git-send-email-yamada.masahiro@socionext.com> References: <1497330250-17348-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Recent versions of this IP support automatic erased page detection. If an erased page is detected on reads, the controller does not set INTR__ECC_UNCOR_ERR, but INTR__ERASED_PAGE. The detection of erased pages is based on the number of zeros in a page; if the number of zeros is less than the value in the field ERASED_THRESHOLD, the page is assumed as erased. Please note ERASED_THRESHOLD specifies the number of zeros in a _page_ instead of an ECC chunk. Moreover, the controller does not provide a way to know the actual number of bitflips. Actually, an erased page (all 0xff) is not an ECC correctable pattern on the Denali ECC engine. In other words, there may be overlap between the following two: [1] a bit pattern reachable from a valid payload + ECC pattern within ecc.strength bitflips [2] a bit pattern reachable from an erased state (all 0xff) within ecc.strength bitflips So, this feature may intercept ECC correctable patterns, then replace [1] with [2]. After all, this feature can work safely only when ECC_THRESHOLD == 1, i.e. detect erased pages without any bitflips. This should be the case most of the time. If there is a bitflip or more, the driver will fallback to the software method by using nand_check_erased_ecc_chunk(). Strangely enough, the driver still has to fill the buffer with 0xff in case of INTR__ERASED_PAGE because the ECC correction engine has already manipulated the data in the buffer before it judges erased pages. Signed-off-by: Masahiro Yamada --- Changes in v6: - memset(buf, 0xff, size) is necessary even if the page is completely erased (all 0xff), strangely. Changes in v5: - Set ECC_THRESHOLD to 1 Changes in v4: None Changes in v3: None Changes in v2: - Newly added drivers/mtd/nand/denali.c | 9 ++++++++- drivers/mtd/nand/denali.h | 5 +++++ 2 files changed, 13 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index d58ea17c0a69..1ded7cc00b1a 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -552,6 +552,9 @@ static int denali_pio_read(struct denali_nand_info *denali, void *buf, if (!(irq_status & INTR__PAGE_XFER_INC)) return -EIO; + if (irq_status & INTR__ERASED_PAGE) + memset(buf, 0xff, size); + return irq_status & ecc_err_mask ? -EBADMSG : 0; } @@ -627,6 +630,9 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, denali_enable_dma(denali, false); dma_sync_single_for_cpu(denali->dev, dma_addr, size, dir); + if (irq_status & INTR__ERASED_PAGE) + memset(buf, 0xff, size); + return ret; } @@ -1397,7 +1403,8 @@ int denali_init(struct denali_nand_info *denali) "chosen ECC settings: step=%d, strength=%d, bytes=%d\n", chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); - iowrite32(chip->ecc.strength, denali->flash_reg + ECC_CORRECTION); + iowrite32(MAKE_ECC_CORRECTION(chip->ecc.strength, 1), + denali->flash_reg + ECC_CORRECTION); iowrite32(mtd->erasesize / mtd->writesize, denali->flash_reg + PAGES_PER_BLOCK); iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index f5da52f09e34..657a794af695 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -110,6 +110,10 @@ #define ECC_CORRECTION 0x1b0 #define ECC_CORRECTION__VALUE GENMASK(4, 0) +#define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16) +#define MAKE_ECC_CORRECTION(val, thresh) \ + (((val) & (ECC_CORRECTION__VALUE)) | \ + (((thresh) << 16) & (ECC_CORRECTION__ERASE_THRESHOLD))) #define READ_MODE 0x1c0 #define READ_MODE__VALUE GENMASK(3, 0) @@ -233,6 +237,7 @@ #define INTR__RST_COMP BIT(13) #define INTR__PIPE_CMD_ERR BIT(14) #define INTR__PAGE_XFER_INC BIT(15) +#define INTR__ERASED_PAGE BIT(16) #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)