From patchwork Fri Jun 9 14:16:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 103509 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp218589qgd; Fri, 9 Jun 2017 06:49:46 -0700 (PDT) X-Received: by 10.98.49.198 with SMTP id x189mr41583817pfx.65.1497016186213; Fri, 09 Jun 2017 06:49:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497016186; cv=none; d=google.com; s=arc-20160816; b=RksOXh+/9RZfNtp+DiXbR/aTKz3pOzzHroSixWY0GYQIKpBxuyaR+xhqzVWlgjS0zQ Yd9wQWeH8ZMki5anqQlhxaamwmpb50Pi1V6/UHsQjKRU7WIJijO/t7G5Fc8tq0SGHVBM qUDhG80sEIfKCmX+oOhIR+3HQfDWkOo+einsPRMgW8Te+EZViReofIXas8N/dnMwyimM cisxb/lelEGON7oqpP2+qKeyt0dRNqAOkNlnrGvBm+J9Us1rdAMbK2qoXPjRycGWh8A+ 7ok/qxgpKKZP5mcDgyLzSF+TH8xzZzxXuAsyPdwv+rj1RbwlDhA2uezY3K3ta7uvBetW 3hLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=3L1+rwfRvP4OxPdFuh8LJ/TPjnUh8XvPy2tD2k79PaQ=; b=lS0W0hQos48b7bxEfTOHyqazn5g4sioFL8C1uOuGyQa21hj5p5DxFNjHYFTwjeyEt6 agZVBIwdg4oOIeCVAewKWh0ATWHajFK2F4ckzyZjx3FbspRPBp4UwC3wM7Upb0lnWTkC TNe7c0z9hZkA3/sbctaNSbMjEZYLDGaA+xQFhEp1JFdM+4AB4kYDPzr0zEc1CAx7IbZc dp2gQ7CTohirChjyWajhi/PERNReuHgk8xT8ZOtU4y3gP9Txm2ae2/kD+OtvjQEwyiBL JgJaQJzCYO5KZ21Z/rcFXQK2+8WQ15TqM0WQL+23DML/PtUtJaFjjx5Wrf/OhYgSPTX/ w43g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 60si1016338plb.445.2017.06.09.06.49.45; Fri, 09 Jun 2017 06:49:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751657AbdFINt1 (ORCPT + 25 others); Fri, 9 Jun 2017 09:49:27 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7791 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751649AbdFINt0 (ORCPT ); Fri, 9 Jun 2017 09:49:26 -0400 Received: from 172.30.72.56 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.56]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AQA55107; Fri, 09 Jun 2017 21:48:46 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Fri, 9 Jun 2017 21:48:33 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v5 22/23] scsi: hisi_sas: add v3 code to fill some more hw function pointers Date: Fri, 9 Jun 2017 22:16:35 +0800 Message-ID: <1497017796-105067-23-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497017796-105067-1-git-send-email-john.garry@huawei.com> References: <1497017796-105067-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0202.593AA74B.0163, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 6a6c5ffee44e909e4df6b4627ca89727 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to fill the interface of phy_hard_reset, phy_get_max_linkrate, and phy enable/disable. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 63a74a0..3688051 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -195,6 +195,8 @@ #define TXID_AUTO (PORT_BASE + 0xb8) #define CT3_OFF 1 #define CT3_MSK (0x1 << CT3_OFF) +#define TX_HARDRST_OFF 2 +#define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) @@ -664,6 +666,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); } +static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + + cfg &= ~PHY_CFG_ENA_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); +} + static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { config_id_frame_v3_hw(hisi_hba, phy_no); @@ -671,6 +681,11 @@ static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) enable_phy_v3_hw(hisi_hba, phy_no); } +static void stop_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + disable_phy_v3_hw(hisi_hba, phy_no); +} + static void start_phys_v3_hw(struct hisi_hba *hisi_hba) { int i; @@ -679,6 +694,26 @@ static void start_phys_v3_hw(struct hisi_hba *hisi_hba) start_phy_v3_hw(hisi_hba, i); } +static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; + u32 txid_auto; + + stop_phy_v3_hw(hisi_hba, phy_no); + if (phy->identify.device_type == SAS_END_DEVICE) { + txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); + hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, + txid_auto | TX_HARDRST_MSK); + } + msleep(100); + start_phy_v3_hw(hisi_hba, phy_no); +} + +enum sas_linkrate phy_get_max_linkrate_v3_hw(void) +{ + return SAS_LINK_RATE_12_0_GBPS; +} + static void phys_init_v3_hw(struct hisi_hba *hisi_hba) { start_phys_v3_hw(hisi_hba); @@ -1967,6 +2002,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) .start_delivery = start_delivery_v3_hw, .slot_complete = slot_complete_v3_hw, .phys_init = phys_init_v3_hw, + .phy_enable = enable_phy_v3_hw, + .phy_disable = disable_phy_v3_hw, + .phy_hard_reset = phy_hard_reset_v3_hw, + .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, }; static struct Scsi_Host *