From patchwork Wed Jun 7 11:52:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 103251 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp1716141obh; Wed, 7 Jun 2017 04:59:16 -0700 (PDT) X-Received: by 10.84.174.67 with SMTP id q61mr27347275plb.97.1496836756652; Wed, 07 Jun 2017 04:59:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496836756; cv=none; d=google.com; s=arc-20160816; b=b4eNCIvK4p3GqjDkUY6uMwwsYGSBLIYlppBW8lUNJml1did10sBDocv+9a/U5vm2wp 2Ihv5+/kORr4cwnoQ5RZthgg8aY7aHhLgVHaPD661tPz5JyNJpCgN7J5g7JWoyG1KH/b apUH4WkLwojc5OO1BTyVrzJYP0vE0ntf8zjw+mafms1qNfnToH0W77Sflar4lUFYKSkh 71GDwlYJq0slkY+AgPHs4VhvhU73cgyxBu7dy76vd9o75D1EzMAM4iSNgazeuVsps/Lb fNYqzCm13ZCnjbqy7o40OtyqD/MuhSN6Dyjaa+MrQlSkTT1xRwpo65kXENEkWCzWoNJX GRIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=NOvNx5hl2aVmS0yPYHowxukHg/fjLu4rQqDitN+B9Gc=; b=UPOb/u3wJ0BPy/F+tCw1N1N/p2EPC7FaFYTcDqdhiqY8d5yyJr7FyLXrk7ufzjca/q fh1pTSLFmgWJtPhVrAvfzYakvfXYai6G1neFWN1MXhA5QaJcEjmUBhuXdcbqGQddgh7G L3kDAPjbf25+FIPYGIBjI9ofXy0+x6RrQbaD0wyXzsRX2hYr7Mh+VTN9xbgd2ZJxjWnx RsZUHdONOy6oWuf67Z44XBgAYZmdzmD7vqFOuwiELAoqIedVgvtJxRKjFAV/FmTN5ERl MJe8CrDTOf4cDqU3hzVOfv8bYHcFYg4BVGx+D4AOxAJi6EqQ52+EDufe0Zb/eHCNZ+vE BwoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a187si1589687pge.160.2017.06.07.04.59.16; Wed, 07 Jun 2017 04:59:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751868AbdFGL7J (ORCPT + 25 others); Wed, 7 Jun 2017 07:59:09 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:42481 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751550AbdFGLzY (ORCPT ); Wed, 7 Jun 2017 07:55:24 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id v57BqjZT014276; Wed, 7 Jun 2017 20:52:50 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v57BqjZT014276 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1496836371; bh=NOvNx5hl2aVmS0yPYHowxukHg/fjLu4rQqDitN+B9Gc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LNLOCTbmUPCd51fs2BJphbmUp+f/0N6jdBmJb/nzi6HHahfYlTjS8cmPsRok94SAp /v4ISRfN0H5lgfu7v12onNUYOr+VXbT041rlQq7MOBp+yZ1GkNsI+dTfLJhbrWyb7H O9UkSY5fC/k6TNSxMCXjnNElQccjtQCLgS2Yt0oza48vquzUBlLALcGihMcS+7PCHm hMXSa0ilEeVm2x92VesCJrl8Q/hZS+5lbwEV6z8oXXOxhxCMkcsvSQoXTVg2ITwDgP NU6iqOXfSXsmzlyjX1CrWCLZFgKrqIdJYXAr7FH5w93XcamPWs4BFYb5mQn61VnlVQ 9P2+WFb8UV0FQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger Subject: [PATCH v5 04/23] mtd: nand: denali: remove Toshiba and Hynix specific fixup code Date: Wed, 7 Jun 2017 20:52:13 +0900 Message-Id: <1496836352-8016-5-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496836352-8016-1-git-send-email-yamada.masahiro@socionext.com> References: <1496836352-8016-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Denali IP can automatically detect device parameters such as page size, oob size, device width, etc. and this driver currently relies on it. However, this hardware function is known to be problematic. [1] Due to a hardware bug, various misdetected cases were reported. That is why get_toshiba_nand_para() and get_hynix_nand_para() exist to fix-up the misdetected parameters. It is not realistic to add a new NAND device to the *black list* every time we are hit by a misdetected case. We would never be able to guarantee that all cases are covered. [2] Because this feature is unreliable, it is disabled on some platforms. The nand_scan_ident() detects device parameters in a more tested way. The hardware should not set the device parameter registers in a different, unreliable way. Instead, set the parameters from the nand_scan_ident() back to the registers. Signed-off-by: Masahiro Yamada --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None drivers/mtd/nand/denali.c | 40 ++++++---------------------------------- 1 file changed, 6 insertions(+), 34 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 0fff11faf603..991924b9ae2c 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -337,36 +337,6 @@ static void get_samsung_nand_para(struct denali_nand_info *denali, } } -static void get_toshiba_nand_para(struct denali_nand_info *denali) -{ - /* - * Workaround to fix a controller bug which reports a wrong - * spare area size for some kind of Toshiba NAND device - */ - if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && - (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) - iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); -} - -static void get_hynix_nand_para(struct denali_nand_info *denali, - uint8_t device_id) -{ - switch (device_id) { - case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ - case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ - iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); - iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); - iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); - iowrite32(0, denali->flash_reg + DEVICE_WIDTH); - break; - default: - dev_warn(denali->dev, - "Unknown Hynix NAND (Device ID: 0x%x).\n" - "Will use default parameter values instead.\n", - device_id); - } -} - /* * determines how many NAND chips are connected to the controller. Note for * Intel CE4100 devices we don't support more than one device. @@ -453,10 +423,6 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) return FAIL; } else if (maf_id == 0xEC) { /* Samsung NAND */ get_samsung_nand_para(denali, device_id); - } else if (maf_id == 0x98) { /* Toshiba NAND */ - get_toshiba_nand_para(denali); - } else if (maf_id == 0xAD) { /* Hynix NAND */ - get_hynix_nand_para(denali, device_id); } dev_info(denali->dev, @@ -1622,6 +1588,12 @@ int denali_init(struct denali_nand_info *denali) chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); iowrite32(chip->ecc.strength, denali->flash_reg + ECC_CORRECTION); + iowrite32(mtd->erasesize / mtd->writesize, + denali->flash_reg + PAGES_PER_BLOCK); + iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, + denali->flash_reg + DEVICE_WIDTH); + iowrite32(mtd->writesize, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); + iowrite32(mtd->oobsize, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); iowrite32(chip->ecc.size, denali->flash_reg + CFG_DATA_BLOCK_SIZE); iowrite32(chip->ecc.size, denali->flash_reg + CFG_LAST_DATA_BLOCK_SIZE);