From patchwork Wed Jun 7 11:52:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 103242 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp1715319obh; Wed, 7 Jun 2017 04:57:07 -0700 (PDT) X-Received: by 10.84.238.139 with SMTP id v11mr27939292plk.182.1496836627516; Wed, 07 Jun 2017 04:57:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496836627; cv=none; d=google.com; s=arc-20160816; b=ux48uVWdkVhnc/knAjWRqUHdKgrDrqs9Trjn24bULwU2CbAH98onjRLuZkCJL7MbCi De897L3RJiiXn850KYkMbA4YcAhyauO2g7kj9fmCiQJegQejkxULq9ob9Q0AKKlAw92u lRThFffPb1oStGm/nRJr89qc0Pg1H8cx/lj05RnB+/nulv4KUjwPjl4f9KMbigQZyaOh 9lNWnRg0tY4iFMUolWl9YmyMxoWPJx1ZBud56eylGpAlwCRDNdpUAWMBJM6okjBF4Au6 wt719GUXF6dykHGKNclB+t/htuhA2DYtBezzOcg4McAsSe+gxShFJOZrA9WOlPjVrLAc 94Gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=0FwFRQi7EAKQabrKJ5ddlEfq5+0GR43mgsG5+Kxm0kw=; b=iCdJ8rm64M7/b2+6p5SctoXq1RG2VvxqdNStiiQBrUg1OSfVDuNYuSvdUowf5U/m/S 34gryiqfguRM3Ybpj3uTZMiiEvO3cHlZyt2kEa+j/jjMp+q2eeuUFAwBg3Js5HKBFEXC nkp0Hdb9wql1wDU8bts0QhIFCfGgHM4L3pAcZHXea741BWFmdLy8xzqMS5pJ5wQ1Uvk6 XFagPpwF0yCD2PNSsJOUJdONnvUmrRI7tXYmwPknvZ+COBR09lolviOtMYnSfKex39Qb RAunT/p2z+QU4tOZWTjYxrMj0TlK8UorgJwEyKT78An5yL/LrUuvTX9njCGRxO5WlzkY ZwAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l1si1540778pld.70.2017.06.07.04.57.07; Wed, 07 Jun 2017 04:57:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751840AbdFGL4t (ORCPT + 25 others); Wed, 7 Jun 2017 07:56:49 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:42698 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751666AbdFGLzb (ORCPT ); Wed, 7 Jun 2017 07:55:31 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id v57BqjZj014276; Wed, 7 Jun 2017 20:53:09 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v57BqjZj014276 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1496836390; bh=0FwFRQi7EAKQabrKJ5ddlEfq5+0GR43mgsG5+Kxm0kw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YX+L4IqMaTQWMDppAh6QfkyG79CTRZK/PyTuX/RGcAkc5A4gJFnvA18ztm1uGcU6l NL1MyhLi7HkbHTYaQBZ4RMqN0GsQvOjU5zrJTxt7wTWmiKrAUardY3UWKWUHsR6Icd OgPb3rhJKBOhbgUtLaJl5vcj7AAekWiTEHVJQsAVFb4+fC25arbVKGIsNl5NnIR7wi 2eEOEDfRZmrEnWL3db6yuF4P6Y+/qb7kJPp3NKZ4c2RkZp30YaaWDvg3GCt2ic4Jyk GGeNu4mqfXgKvxOAE0ukOlVYpIab308seXdc8xorgCgCaes2vbxE6HekdmSgt59l1E nRCdZ8vVP5MsA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger Subject: [PATCH v5 20/23] mtd: nand: denali: support hardware-assisted erased page detection Date: Wed, 7 Jun 2017 20:52:29 +0900 Message-Id: <1496836352-8016-21-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496836352-8016-1-git-send-email-yamada.masahiro@socionext.com> References: <1496836352-8016-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Recent versions of this IP support automatic erased page detection. If an erased page is detected on reads, the controller does not set INTR__ECC_UNCOR_ERR, but INTR__ERASED_PAGE. The detection of erased page is based on the number of zeros in a page; if the number of zeros is less than the value in the field ERASED_THRESHOLD, the page is assumed as erased. Please note ERASED_THRESHOLD specifies the number of zeros in a _page_ instead of an ECC chunk. Moreover, the controller does not provide a way to know the actual number of bitflips. Actually, an erased page (all 0xff) is not an ECC correctable pattern on the Denali ECC engine. In other words, there is overlap between the following two: [1] a bit pattern reachable from a valid payload + ECC pattern within ecc.strength bitflips [2] a bit pattern reachable from an erased state (all 0xff) within ecc.strength bitflips So, this feature may intercept ECC correctable patterns, then replace [1] with [2]. After all, this feature can work safely only when ECC_THRESHOLD == 1, i.e. detect erased pages without any bitflips. This should be the case most of the time. If there are some bitflips, the driver will fallback to the software method by using nand_check_erased_ecc_chunk(). Signed-off-by: Masahiro Yamada --- Changes in v5: - Set ECC_THRESHOLD to 1 Changes in v4: None Changes in v3: None Changes in v2: - Newly added drivers/mtd/nand/denali.c | 3 ++- drivers/mtd/nand/denali.h | 5 +++++ 2 files changed, 7 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index dcadf9655d7a..90c702b9f14c 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1446,7 +1446,8 @@ int denali_init(struct denali_nand_info *denali) "chosen ECC settings: step=%d, strength=%d, bytes=%d\n", chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); - iowrite32(chip->ecc.strength, denali->flash_reg + ECC_CORRECTION); + iowrite32(MAKE_ECC_CORRECTION(chip->ecc.strength, 1), + denali->flash_reg + ECC_CORRECTION); iowrite32(mtd->erasesize / mtd->writesize, denali->flash_reg + PAGES_PER_BLOCK); iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index f5da52f09e34..657a794af695 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -110,6 +110,10 @@ #define ECC_CORRECTION 0x1b0 #define ECC_CORRECTION__VALUE GENMASK(4, 0) +#define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16) +#define MAKE_ECC_CORRECTION(val, thresh) \ + (((val) & (ECC_CORRECTION__VALUE)) | \ + (((thresh) << 16) & (ECC_CORRECTION__ERASE_THRESHOLD))) #define READ_MODE 0x1c0 #define READ_MODE__VALUE GENMASK(3, 0) @@ -233,6 +237,7 @@ #define INTR__RST_COMP BIT(13) #define INTR__PIPE_CMD_ERR BIT(14) #define INTR__PAGE_XFER_INC BIT(15) +#define INTR__ERASED_PAGE BIT(16) #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)