From patchwork Wed Jun 7 11:52:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 103237 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp1714816obh; Wed, 7 Jun 2017 04:55:43 -0700 (PDT) X-Received: by 10.98.5.130 with SMTP id 124mr30824999pff.209.1496836543743; Wed, 07 Jun 2017 04:55:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496836543; cv=none; d=google.com; s=arc-20160816; b=fog3SckWSHwC5ertKTD/tyURdwEZTUhtdv/ue1JjCiPVSQF8yC16U6CfrZlT+xqSq/ h6JDoqPoIXJ6mq2A1nPe28HmvlhUn/ecZfHAdfZSRir/Fi4yTBTkla4NokK3bEeCEVAS krN5AtlIoiY7z9deEhircNxWIo2lN2WMQboIV3r14Mx2/pt9oD3KiJoMM6310O7wohKv tN4ucdMwga3LmQIxLqTO17n273t3hfne9Pm5DdZ0LHjqeNQOdk13YL57PZwEJvXy277u MruSp7+sqpKbK7eV+D9iYXs2B3K9qU+Ucy1iFt5k7Z37s50Z+uyeAxVVAt9Mfr4SyOs9 1Knw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=aAEh++VVVxJI05TySbNB12PLkWL7nCG73zseBkVCTiA=; b=nFjAUYMDwbVpE0a2nmMWUUr2Nb7s1WhkbpsjxCSfk1EU3yH07hc4qjNqbvYEM/dnJz VPgvRhJspYKioVNptkuXbtQCwKokCMqp3pg6+hDtrbN/mzWwHYkVOv4X5xltxYaCJqOU RJih18Wk7fmO/EmT/8VDxTEefLVUiQdppLmNvAuGAD3ijcIqs74Ygwe9NLhrLTRoAh2W M7zDgfy760JU7TZTrYuQGyjgZHcvOE1e1toGssQFAUfDjYXOxO0sXzx7CoErvsuOyLfJ rtpDe5DtO+e6iRpedtPZYAD1B6RuS6p23znAsC4155K4g+5wOsJmTp6m/5Dm1BUuNklj qilw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e186si1569105pgc.163.2017.06.07.04.55.43; Wed, 07 Jun 2017 04:55:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751734AbdFGLzj (ORCPT + 25 others); Wed, 7 Jun 2017 07:55:39 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:42824 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751707AbdFGLze (ORCPT ); Wed, 7 Jun 2017 07:55:34 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id v57BqjZh014276; Wed, 7 Jun 2017 20:53:07 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v57BqjZh014276 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1496836388; bh=aAEh++VVVxJI05TySbNB12PLkWL7nCG73zseBkVCTiA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K2xQ8pnf+ptWPNYEzmQGzXbd7wRgyUqVxDXa4maz1PmukTbGOHwx/Ew3tFoCl4J5q 819o4Tq32YzNncE2dZ81J5jOm0NEDlM9ogROyNDJ3wjWpCWsuwpfITZ2Tsqm6pG4nJ +/yOkCsKatta1hfkt0an719DAW+T3YO2sQrS0Wp3IjAXnJ+f5c0qKWaxSzXYHt0TDP NwEAluWvryH0yX3VQQa0bLsfaloU6a18RYBRuLiYqD4tK4oCd8ec+WL0FYlvBD1yPU nIsKhMN6afhLtCwJJKAJmYgNNJxr5I/EnLDDQrFcgAWtNI7s2nGwML6WFCsw+MC17T tvTr58BiDjHyg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger Subject: [PATCH v5 18/23] mtd: nand: denali: use flag instead of register macro for direction Date: Wed, 7 Jun 2017 20:52:27 +0900 Message-Id: <1496836352-8016-19-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496836352-8016-1-git-send-email-yamada.masahiro@socionext.com> References: <1496836352-8016-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It is not a good idea to re-use macros that represent a specific register bit field for the transfer direction. It is true that bit 8 indicates the direction for the MAP10 pipeline operation and the data DMA operation, but this is not valid across the IP. Use a simple flag (write: 1, read: 0) for the direction. Signed-off-by: Masahiro Yamada --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: - Newly added drivers/mtd/nand/denali.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index d8d207125701..735dcbdbb1b4 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -53,9 +53,6 @@ static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) #define MAIN_ACCESS 0x42 #define MAIN_SPARE_ACCESS 0x43 -#define DENALI_READ 0 -#define DENALI_WRITE 0x100 - #define DENALI_NR_BANKS 4 /* @@ -284,7 +281,7 @@ static int denali_dev_ready(struct mtd_info *mtd) */ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, int page, bool ecc_en, bool transfer_spare, - int access_type, int op) + int access_type, int write) { int status = PASS; uint32_t addr, cmd; @@ -295,17 +292,17 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, int page, addr = BANK(denali->flash_bank) | page; - if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { + if (write && access_type != SPARE_ACCESS) { cmd = MODE_01 | addr; iowrite32(cmd, denali->flash_mem); - } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { + } else if (write && access_type == SPARE_ACCESS) { /* read spare area */ cmd = MODE_10 | addr; index_addr(denali, cmd, access_type); cmd = MODE_01 | addr; iowrite32(cmd, denali->flash_mem); - } else if (op == DENALI_READ) { + } else { /* setup page read request for access type */ cmd = MODE_10 | addr; index_addr(denali, cmd, access_type); @@ -367,7 +364,7 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) int status = 0; if (denali_send_pipeline_cmd(denali, page, false, false, SPARE_ACCESS, - DENALI_WRITE) == PASS) { + 1) == PASS) { write_data_to_flash_mem(denali, buf, mtd->oobsize); /* wait for operation to complete */ @@ -392,7 +389,7 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) uint32_t irq_status, addr, cmd; if (denali_send_pipeline_cmd(denali, page, false, true, SPARE_ACCESS, - DENALI_READ) == PASS) { + 0) == PASS) { read_data_from_flash_mem(denali, buf, mtd->oobsize); /* @@ -578,7 +575,7 @@ static void denali_enable_dma(struct denali_nand_info *denali, bool en) } static void denali_setup_dma64(struct denali_nand_info *denali, - dma_addr_t dma_addr, int page, int op) + dma_addr_t dma_addr, int page, int write) { uint32_t mode; const int page_count = 1; @@ -591,7 +588,8 @@ static void denali_setup_dma64(struct denali_nand_info *denali, * 1. setup transfer type, interrupt when complete, * burst len = 64 bytes, the number of pages */ - index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count); + index_addr(denali, mode, + 0x01002000 | (64 << 16) | (write << 8) | page_count); /* 2. set memory low address */ index_addr(denali, mode, dma_addr); @@ -601,7 +599,7 @@ static void denali_setup_dma64(struct denali_nand_info *denali, } static void denali_setup_dma32(struct denali_nand_info *denali, - dma_addr_t dma_addr, int page, int op) + dma_addr_t dma_addr, int page, int write) { uint32_t mode; const int page_count = 1; @@ -611,7 +609,7 @@ static void denali_setup_dma32(struct denali_nand_info *denali, /* DMA is a four step process */ /* 1. setup transfer type and # of pages */ - index_addr(denali, mode | page, 0x2000 | op | page_count); + index_addr(denali, mode | page, 0x2000 | (write << 8) | page_count); /* 2. set memory high address bits 23:8 */ index_addr(denali, mode | ((dma_addr >> 16) << 8), 0x2200); @@ -624,12 +622,12 @@ static void denali_setup_dma32(struct denali_nand_info *denali, } static void denali_setup_dma(struct denali_nand_info *denali, - dma_addr_t dma_addr, int page, int op) + dma_addr_t dma_addr, int page, int write) { if (denali->caps & DENALI_CAP_DMA_64BIT) - denali_setup_dma64(denali, dma_addr, page, op); + denali_setup_dma64(denali, dma_addr, page, write); else - denali_setup_dma32(denali, dma_addr, page, op); + denali_setup_dma32(denali, dma_addr, page, write); } /* @@ -668,7 +666,7 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip, denali_reset_irq(denali); denali_enable_dma(denali, true); - denali_setup_dma(denali, addr, page, DENALI_WRITE); + denali_setup_dma(denali, addr, page, 1); /* wait for operation to complete */ irq_status = denali_wait_for_irq(denali, irq_mask); @@ -750,7 +748,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); denali_reset_irq(denali); - denali_setup_dma(denali, addr, page, DENALI_READ); + denali_setup_dma(denali, addr, page, 0); /* wait for operation to complete */ irq_status = denali_wait_for_irq(denali, irq_mask); @@ -793,7 +791,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); denali_reset_irq(denali); - denali_setup_dma(denali, addr, page, DENALI_READ); + denali_setup_dma(denali, addr, page, 0); /* wait for operation to complete */ irq_status = denali_wait_for_irq(denali, irq_mask);