From patchwork Mon Jun 5 23:21:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 103111 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp1009064obh; Mon, 5 Jun 2017 16:27:42 -0700 (PDT) X-Received: by 10.84.178.4 with SMTP id y4mr18186376plb.158.1496705262502; Mon, 05 Jun 2017 16:27:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496705262; cv=none; d=google.com; s=arc-20160816; b=MrJgCH1Rl2YnP9sYnlO+s0uijqmUxVePQIazCAx1nNYBSwwED2eRxGnPtEfQctKr0k stkxqnt8XyVf2lAgAkamffnY+blhPsjPNqA07YzxlSmBxG1sGIgQ8/eRp16APJ/mnlC9 1/JvNwOfp/6f0BUD0nkSgYY5YWUyW++e7IDrXZoxra6WUfxMB+r1c75gyk+Mwdo7HRhP tn1uiW1z2OyywLjCR37kSmhF6hKCcNAhXyb5GU21NwfJC54ESPE9WTcUpb5ARxtHxuGJ SBRkDK1vlSOHdW5p+avBEkzmWuDXN39her9W43VdQZIYrVzGsD48KDuKkrJZvfBTdRbK ZxLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=FHqmp2kVG0rcDHKXNVG+Q/0fotjs/HIOXTrh55tzCqk=; b=a1eQqrYSTbhybt8rKBDdBHESngyGJLZr3hcCbF0bSDgSBeZEqH/wkPjOCEIvqNxLyg lk8C3nDUQz9ZNShxkmjatkgFuL9j7me7yc5rwxRh+slj7nuZMu+s0hQcNeVE6Pds54KC frg6TKwLiOYzF/W/ykcoyonMEuPqdoqbSIVtx9H52RKCv1FD0DnP1YYN4ak7DKK8ZGWg GFv2ikLP8F5UKzaFTJzx8gWjRoIm3AFmAlw5s/y7TpkLoMmSM1eEvuhJr6DvdpLm3h8T 6HjmRMK+UP6JYD3xi72vunIqHHQUwdwvU9KUz9f0KPSy5OPx06teiG676ASk2goVTnnL pr1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 84si31596096pfa.395.2017.06.05.16.27.42; Mon, 05 Jun 2017 16:27:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751342AbdFEXZV (ORCPT + 25 others); Mon, 5 Jun 2017 19:25:21 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:32119 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751264AbdFEXZQ (ORCPT ); Mon, 5 Jun 2017 19:25:16 -0400 Received: from grover.sesame (FL1-118-110-19-204.osk.mesh.ad.jp [118.110.19.204]) (authenticated) by conuserg-10.nifty.com with ESMTP id v55NMD5p004412; Tue, 6 Jun 2017 08:22:45 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v55NMD5p004412 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1496704966; bh=FHqmp2kVG0rcDHKXNVG+Q/0fotjs/HIOXTrh55tzCqk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Jtqs8CjW4MdWgd/Np4CTvKbJHtRuvXbcwO7ONIGFtpwzrP++SJuXKBxKyeq/m6whd 8zcpkr2hEoXR9C5VZr/SkiMtkE3sS3l3Chxga2X+sDPZ8QUdOiIowOzwuT7E17iTke Pg7m7Nik6HzQHhvfXpp/sAvpqQlvrIjGWIg3AMuSivwg49uVCMkJ+ObAhNEtBrtULz 2S2G/0VAIKchm/HXUJWueoMUy5KLuu2Avv9DvKrUUvvyZF+WfloJqfKu6aIIT3E1p4 t00UpTMkLq10INj1W3dOQutT7se2E7Aaq4YWfUUlCFsTqoJcq1pTbPxAV6cjxQ0rP0 X3lAUR0oX4kWA== X-Nifty-SrcIP: [118.110.19.204] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger Subject: [PATCH v4 15/23] mtd: nand: denali: fix bank reset function to detect the number of chips Date: Tue, 6 Jun 2017 08:21:54 +0900 Message-Id: <1496704922-12261-16-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496704922-12261-1-git-send-email-yamada.masahiro@socionext.com> References: <1496704922-12261-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The nand_scan_ident() iterates over maxchips, and calls nand_reset() for each. This driver currently passes the maximum number of banks (=chip selects) supported by the controller as maxchips. So, maxchips is typically 4 or 8. Usually, less number of NAND chips are connected to the controller. This can be a problem for ONFi devices. Now, this driver implements ->setup_data_interface() hook, so nand_setup_data_interface() issues Set Features (0xEF) command, which waits until the chip returns R/B# response. If no chip there, we know it never happens, but the driver still ends up with waiting for a long time. It will finally bail-out with timeout error and the driver will work with existing chips, but unnecessary wait will give a bad user experience. The denali_nand_reset() polls the INTR__RST_COMP and INTR__TIME_OUT bits, but they are always set even if not NAND chip is connected to that bank. To know the chip existence, INTR__INT_ACT bit must be checked; this flag is set only when R/B# is toggled. Since the Reset (0xFF) command toggles the R/B# pin, this can be used to know the actual number of chips, and update denali->max_banks. Signed-off-by: Masahiro Yamada --- Boris mentioned this information can be retrieved from DT (http://patchwork.ozlabs.org/patch/745118/), but I'd like to take time for controller/chip decoupling. I am tackling on that, but not completed yet. I believe this commit stands for denali_pci, at least I do not know how to get the number of chips from PCI. Changes in v4: - Reword commit-log Changes in v3: None Changes in v2: - Newly added drivers/mtd/nand/denali.c | 52 +++++++++++++++++++++-------------------------- 1 file changed, 23 insertions(+), 29 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 083dfc7..775387e 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -85,33 +85,6 @@ static void index_addr(struct denali_nand_info *denali, iowrite32(data, denali->flash_mem + 0x10); } -/* Reset the flash controller */ -static uint16_t denali_nand_reset(struct denali_nand_info *denali) -{ - int i; - - for (i = 0; i < denali->max_banks; i++) - iowrite32(INTR__RST_COMP | INTR__TIME_OUT, - denali->flash_reg + INTR_STATUS(i)); - - for (i = 0; i < denali->max_banks; i++) { - iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); - while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & - (INTR__RST_COMP | INTR__TIME_OUT))) - cpu_relax(); - if (ioread32(denali->flash_reg + INTR_STATUS(i)) & - INTR__TIME_OUT) - dev_dbg(denali->dev, - "NAND Reset operation timed out on bank %d\n", i); - } - - for (i = 0; i < denali->max_banks; i++) - iowrite32(INTR__RST_COMP | INTR__TIME_OUT, - denali->flash_reg + INTR_STATUS(i)); - - return PASS; -} - /* * Use the configuration feature register to determine the maximum number of * banks that the hardware supports. @@ -999,7 +972,28 @@ static int denali_setup_data_interface(struct mtd_info *mtd, return 0; } -/* Initialization code to bring the device up to a known good state */ +static void denali_reset_banks(struct denali_nand_info *denali) +{ + int i; + + denali_clear_irq_all(denali); + + for (i = 0; i < denali->max_banks; i++) { + iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); + while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & + (INTR__RST_COMP | INTR__TIME_OUT))) + cpu_relax(); + if (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & + INTR__INT_ACT)) + break; + } + + dev_dbg(denali->dev, "%d chips connected\n", i); + denali->max_banks = i; + + denali_clear_irq_all(denali); +} + static void denali_hw_init(struct denali_nand_info *denali) { /* @@ -1019,7 +1013,7 @@ static void denali_hw_init(struct denali_nand_info *denali) denali->bbtskipbytes = ioread32(denali->flash_reg + SPARE_AREA_SKIP_BYTES); detect_max_banks(denali); - denali_nand_reset(denali); + denali_reset_banks(denali); iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->flash_reg + CHIP_ENABLE_DONT_CARE);