From patchwork Sat Jun 3 04:04:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 101299 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp41696qgd; Fri, 2 Jun 2017 21:05:47 -0700 (PDT) X-Received: by 10.98.224.194 with SMTP id d63mr3911377pfm.174.1496462747098; Fri, 02 Jun 2017 21:05:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496462747; cv=none; d=google.com; s=arc-20160816; b=0qIhiC5D2FFGS9driMsGN6haC8r/bMFZOt2wpD1ejb0+QyQT4E2LzBUrESbSoZg8dR 9j97Ghuq2ctqXibIZ4LEtYF9a2IO3tSufiGl4nbcQvcbEL9Gbg2AcdVfNn4Pe8XzoqFh 2go8sz8sSvClI8E/MBPXsBZ2bj2RD/LjUK7ePRCHP2PRYL69OcHHBkKdRC/F7+RWZI8M 9pY+jyRmaMGkUJ2wpFwD/FRqSGR2SbJ8yy2JO6Wix+r0AsxygTnwNToPD2+f165vbh/V 5KzEdMEEtQEYTOqEU+kwbFw6H9lnbMX6kQ+cPCdMDKIm8jriUy7VuTu7nBqXgYv2KWhe /QIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=55v2FwrKIWw69yGXYt0GiWLER3dhCKvhBWxjhILS5lA=; b=ItymKZcB6qSP9IBwHzUSqFjIBKGrmFFf0C+nWCO3HckZjbuOqevqPXl/Doa8i3jhsz mt/nhyPl6iIhZ36ZRHtml/P2AxQDbw3U012QnD3px411RLra3Tj3CIFrbPPjSdGwdOZG ddZRJRZLd+gAfruoo212OMMjJESLAy70gk9h+KGwR/SXnAuSvAT1DVOuXL88TZraGtmw Em8V/b2x7mtLWxBxSyKZKjd7GLcJTuJFZOPUG9cydWuHZXKrd3weuA+0Dxqzvns/CpjL do8k9GR4zaWBx1hgyQAxjF+oJQWyYWMbcxKzpCMwJtxidSHPVUo9yrxlZB3r9LHE0vXD GbGA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 33si1501794plc.304.2017.06.02.21.05.46; Fri, 02 Jun 2017 21:05:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751349AbdFCEFb (ORCPT + 25 others); Sat, 3 Jun 2017 00:05:31 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7302 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751241AbdFCEEk (ORCPT ); Sat, 3 Jun 2017 00:04:40 -0400 Received: from 172.30.72.56 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.56]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APR03903; Sat, 03 Jun 2017 12:04:24 +0800 (CST) Received: from localhost (10.177.23.32) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Sat, 3 Jun 2017 12:04:14 +0800 From: Ding Tianhong To: , , , , , , , , , , , , , , , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v2 2/3] PCI: Enable PCIe Relaxed Ordering if supported Date: Sat, 3 Jun 2017 12:04:06 +0800 Message-ID: <1496462647-7632-3-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1496462647-7632-1-git-send-email-dingtianhong@huawei.com> References: <1496462647-7632-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.5932354B.0018, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 63dd14c2a9e0465dbc74dbd82be0d15c Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PCIe Device Control Register use the bit 4 to indicate that whether the device is permitted to enable relaxed ordering or not. But relaxed ordering is not safe for some platform which could only use strong write ordering, so devices are allowed (but not required) to enable relaxed ordering bit by default. If a platform support relaxed ordering but does not enable it by default, enable it in the PCIe configuration. This allows some device to send TLPs with the relaxed ordering attributes set, which may improve the performance. Signed-off-by: Ding Tianhong --- drivers/pci/pci.c | 42 ++++++++++++++++++++++++++++++++++++++++++ drivers/pci/probe.c | 11 +++++++++++ include/linux/pci.h | 3 +++ 3 files changed, 56 insertions(+) -- 1.9.0 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b01bd5b..f57a374 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4878,6 +4878,48 @@ int pcie_set_mps(struct pci_dev *dev, int mps) EXPORT_SYMBOL(pcie_set_mps); /** + * pcie_set_relaxed_ordering - set PCI Express relexed ordering bit + * @dev: PCI device to query + * + * If possible sets relaxed ordering + */ +int pcie_set_relaxed_ordering(struct pci_dev *dev) +{ + return pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); +} +EXPORT_SYMBOL(pcie_set_relaxed_ordering); + +/** + * pcie_clear_relaxed_ordering - clear PCI Express relexed ordering bit + * @dev: PCI device to query + * + * If possible clear relaxed ordering + */ +int pcie_clear_relaxed_ordering(struct pci_dev *dev) +{ + return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); +} +EXPORT_SYMBOL(pcie_clear_relaxed_ordering); + +/** + * pcie_get_relaxed_ordering - check PCI Express relexed ordering bit + * @dev: PCI device to query + * + * Returns true if relaxed ordering is been set + */ +int pcie_get_relaxed_ordering(struct pci_dev *dev) +{ + u16 v; + + pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); + + return (v & PCI_EXP_DEVCTL_RELAX_EN) >> 4; +} +EXPORT_SYMBOL(pcie_get_relaxed_ordering); + +/** + * pcie_set_mps - set PCI Express maximum payload size +/** * pcie_get_minimum_link - determine minimum link settings of a PCI device * @dev: PCI device to query * @speed: storage for minimum speed diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 19c8950..aeb22b5 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1701,6 +1701,16 @@ static void pci_configure_extended_tags(struct pci_dev *dev) PCI_EXP_DEVCTL_EXT_TAG); } +static void pci_configure_relaxed_ordering(struct pci_dev *dev) +{ + int ret; + + if (dev && (dev->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING)) + pcie_set_relaxed_ordering(dev); + else + pcie_clear_relaxed_ordering(dev); +} + static void pci_configure_device(struct pci_dev *dev) { struct hotplug_params hpp; @@ -1708,6 +1718,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_mps(dev); pci_configure_extended_tags(dev); + pci_configure_relaxed_ordering(dev); memset(&hpp, 0, sizeof(hpp)); ret = pci_get_hp_params(dev, &hpp); diff --git a/include/linux/pci.h b/include/linux/pci.h index e1e8428..84bd6af 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1105,6 +1105,9 @@ int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, void pci_pme_wakeup_bus(struct pci_bus *bus); void pci_d3cold_enable(struct pci_dev *dev); void pci_d3cold_disable(struct pci_dev *dev); +int pcie_set_relaxed_ordering(struct pci_dev *dev); +int pcie_clear_relaxed_ordering(struct pci_dev *dev); +int pcie_get_relaxed_ordering(struct pci_dev *dev); static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)