From patchwork Thu Jun 1 11:03:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 100889 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp700143obc; Thu, 1 Jun 2017 04:05:22 -0700 (PDT) X-Received: by 10.99.163.110 with SMTP id v46mr578562pgn.210.1496315122171; Thu, 01 Jun 2017 04:05:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496315122; cv=none; d=google.com; s=arc-20160816; b=ExZ0bmKxBr1Vz4zqc9qAFQ7STEYzv26+t/88DMxs8/XYdKNSYtcYELy2wyWqZzw13E V7d6XSlolGWd76BagXuI3mob7phSIjCm3ExGGuTk8JRciFSWCt2oL27a8mD4cgnS74Aq g8FM3nf1bVXbbjd0sBYCgzIjNnYr7oI+tzCzAh+3etXo5STV9T3UDouEac8O3q1m9K5f LyeGXigZ++nbTJmo59u1klO7HL2ESPqwhCee8UD6b10oe04DtzsnEKcjDHtTEyRKU0bD 6GtKx/xwpetUIMppOd9yXIif0fc1AkjY38VD3k4XWorhoHbtVrmOkqJFSlHDoIHVOTFF Teew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=7Hv03Nyu0r46z1lYCiYh8l2sfm6cLU6c6GIg0EycaGE=; b=Z9NGs7/FgHxFmfnNqxvSGxz251PtUx8VtFI3ytoQxEUASaW6Ah/gebI4iEMCkJek6f Sfb/ocSqOjDZt7d/Y6E0DnXkf4mLXQh4gD9oT0tGpLW9Rbo3ewJv28KkD4g9A3wEZwYQ pVcXZ4Ckw47EUHOVzH7Q3CWZ2at7Bi6jPsZwzUJk5v5WrbeNckV1pDOSVseGBzu2e6td hEnv/qNK+5JCin8sMT19vlRy2gEYZBZaJYhD2XUJ66KJuRKFEXy0IVpWQ9ibHtwSFBs8 ObW3f4jf0MCFB12geszQl4uBP0mmTQxniYNGUvCvne8iNx/BQRPBw4MQ3J0QETio+CDB FMVg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 66si19647489pfo.368.2017.06.01.04.05.21; Thu, 01 Jun 2017 04:05:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751997AbdFALFA (ORCPT + 25 others); Thu, 1 Jun 2017 07:05:00 -0400 Received: from foss.arm.com ([217.140.101.70]:54520 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751574AbdFALE6 (ORCPT ); Thu, 1 Jun 2017 07:04:58 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 483A215A2; Thu, 1 Jun 2017 04:04:58 -0700 (PDT) Received: from gby.kfn.arm.com (unknown [10.45.48.155]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 726603F578; Thu, 1 Jun 2017 04:04:56 -0700 (PDT) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Joe Perches , Ofir Drang , linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org Subject: [PATCH v2 14/20] staging: ccree: remove custom bitfield macros Date: Thu, 1 Jun 2017 14:03:04 +0300 Message-Id: <1496314993-30229-15-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1496314993-30229-1-git-send-email-gilad@benyossef.com> References: <1496314993-30229-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org With all users removed or re-factored to use the standard kernel bit fields ops we can now drop the custom bit field macros. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/cc_bitops.h | 39 ------------------- drivers/staging/ccree/cc_hw_queue_defs.h | 2 +- drivers/staging/ccree/cc_lli_defs.h | 2 - drivers/staging/ccree/cc_regs.h | 65 +------------------------------- drivers/staging/ccree/ssi_driver.h | 1 - 5 files changed, 2 insertions(+), 107 deletions(-) delete mode 100644 drivers/staging/ccree/cc_bitops.h -- 2.1.4 diff --git a/drivers/staging/ccree/cc_bitops.h b/drivers/staging/ccree/cc_bitops.h deleted file mode 100644 index cbdc1ab..0000000 --- a/drivers/staging/ccree/cc_bitops.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -/*! - * \file cc_bitops.h - * Bit fields operations macros. - */ -#ifndef _CC_BITOPS_H_ -#define _CC_BITOPS_H_ - -#include -#include - -#define BITMASK(mask_size) (((mask_size) < 32) ? \ - ((1UL << (mask_size)) - 1) : 0xFFFFFFFFUL) - -#define BITMASK_AT(mask_size, mask_offset) (BITMASK(mask_size) << (mask_offset)) - -#define BITFIELD_GET(word, bit_offset, bit_size) \ - (((word) >> (bit_offset)) & BITMASK(bit_size)) -#define BITFIELD_SET(word, bit_offset, bit_size, new_val) do { \ - word = ((word) & ~BITMASK_AT(bit_size, bit_offset)) | \ - (((new_val) & BITMASK(bit_size)) << (bit_offset)); \ -} while (0) - -#endif /*_CC_BITOPS_H_*/ diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h b/drivers/staging/ccree/cc_hw_queue_defs.h index e750817..8dc9b6e 100644 --- a/drivers/staging/ccree/cc_hw_queue_defs.h +++ b/drivers/staging/ccree/cc_hw_queue_defs.h @@ -19,8 +19,8 @@ #include -#include "cc_regs.h" #include "dx_crys_kernel.h" +#include /****************************************************************************** * DEFINITIONS diff --git a/drivers/staging/ccree/cc_lli_defs.h b/drivers/staging/ccree/cc_lli_defs.h index 78811aa..851d390 100644 --- a/drivers/staging/ccree/cc_lli_defs.h +++ b/drivers/staging/ccree/cc_lli_defs.h @@ -19,8 +19,6 @@ #include -#include "cc_bitops.h" - /* Max DLLI size * AKA DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE */ diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h index f9d5280..e83938b 100644 --- a/drivers/staging/ccree/cc_regs.h +++ b/drivers/staging/ccree/cc_regs.h @@ -24,7 +24,7 @@ #ifndef _CC_REGS_H_ #define _CC_REGS_H_ -#include "cc_bitops.h" +#include #define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP) #define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \ @@ -35,67 +35,4 @@ #define CC_REG_OFFSET(unit_name, reg_name) \ (DX_BASE_ ## unit_name + DX_ ## reg_name ## _REG_OFFSET) -#define CC_REG_BIT_SHIFT(reg_name, field_name) \ - (DX_ ## reg_name ## _ ## field_name ## _BIT_SHIFT) - -/* Read-Modify-Write a field of a register */ -#define MODIFY_REGISTER_FLD(unitName, regName, fldName, fldVal) \ -do { \ - u32 regVal; \ - regVal = READ_REGISTER(CC_REG_ADDR(unitName, regName)); \ - CC_REG_FLD_SET(unitName, regName, fldName, regVal, fldVal); \ - WRITE_REGISTER(CC_REG_ADDR(unitName, regName), regVal); \ -} while (0) - -/*! Bit fields get */ -#define CC_REG_FLD_GET(unit_name, reg_name, fld_name, reg_val) \ - (DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ? \ - reg_val /*!< \internal Optimization for 32b fields */ : \ - BITFIELD_GET(reg_val, DX_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \ - DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE)) - -/*! Bit fields access */ -#define CC_REG_FLD_GET2(unit_name, reg_name, fld_name, reg_val) \ - (CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ? \ - reg_val /*!< \internal Optimization for 32b fields */ : \ - BITFIELD_GET(reg_val, CC_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \ - CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE)) - -/* yael TBD !!! - * -* all HW includes should start with CC_ and not DX_ !! */ - - -/*! Bit fields set */ -#define CC_REG_FLD_SET( \ - unit_name, reg_name, fld_name, reg_shadow_var, new_fld_val) \ -do { \ - if (DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20) \ - reg_shadow_var = new_fld_val; /*!< \internal Optimization for 32b fields */\ - else \ - BITFIELD_SET(reg_shadow_var, \ - DX_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \ - DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE, \ - new_fld_val); \ -} while (0) - -/*! Bit fields set */ -#define CC_REG_FLD_SET2( \ - unit_name, reg_name, fld_name, reg_shadow_var, new_fld_val) \ -do { \ - if (CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20) \ - reg_shadow_var = new_fld_val; /*!< \internal Optimization for 32b fields */\ - else \ - BITFIELD_SET(reg_shadow_var, \ - CC_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \ - CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE, \ - new_fld_val); \ -} while (0) - -/* Usage example: - u32 reg_shadow = READ_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL)); - CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY0,reg_shadow, 3); - CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY1,reg_shadow, 1); - WRITE_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL), reg_shadow); - */ - #endif /*_CC_REGS_H_*/ diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h index f3df70b..daa9376 100644 --- a/drivers/staging/ccree/ssi_driver.h +++ b/drivers/staging/ccree/ssi_driver.h @@ -40,7 +40,6 @@ /* Registers definitions from shared/hw/ree_include */ #include "dx_reg_base_host.h" #include "dx_host.h" -#define DX_CC_HOST_VIRT /* must be defined before including dx_cc_regs.h */ #include "cc_regs.h" #include "dx_reg_common.h" #include "cc_hal.h"