From patchwork Sun May 28 14:40:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 100617 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1063224qge; Sun, 28 May 2017 07:41:26 -0700 (PDT) X-Received: by 10.98.108.70 with SMTP id h67mr12378935pfc.98.1495982486220; Sun, 28 May 2017 07:41:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495982486; cv=none; d=google.com; s=arc-20160816; b=SbubVOvQ5GZHCpH3gp28VjVSLEQ4ATkWPAJRN/duJFouaYaulsdHBjM4CWhjvrrS8S +//CIKz/ntYsIWZesPu9wkqgAtILQRssZbxIKXjSjGqKBQYFVIdmI5qMRjlv6ahnuDht EbM/p28s9A6t9OMtt2ILzDqi7CxgOO1AyJMyDmVjZI2JRLThpIC8dAXoBLPSK+XNpTXD +LnJbEgQbCqm8PgKdzjpYUgU1aas0QgY1luTOyYeZgTESEyR3hqfHMk3rfTNh8ownRk+ OJUa5Nva8V+D0VyhPIRuyjspjjCW3LZVD12fpFkQJJ6lq291WoYRNhL5lyvf9XRvm46Q jNog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=ILQgw0EnYm6baeIcGDXhYJuSeTKj+4d+6ZAI0oHmPn0=; b=N7SsF1QbukoiIO6iLZUlgvj7QuO2qvlxHHgRLrfbg8UEuJE0aatscMkjQErtjwdY4i lT2/fIS9XVclJD1MB+kUUVXShw5c4JOAXsys/yWyXiqoAsGvjy4QFBSEc0TyB/PEkJ8p DG/JC6qAGu/I8ar7plncVKqL/eAYX85Qu55KbmScqRz9zzJYyY2ENU8V0N0fDpcZK3Qp rclefQjFuU/jfuRZURC7vcsff4+6tKwWU5OnnbBTi4JIyl1/mnmMJAZ9lsyYVEAC8EI5 cRkBZtw0qxxfUmlO84leumDf+XqTptSp9fn1NAeIZCSyyht+lG0T2wbwN+NE/6KQ3OAr jg1Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h83si7521621pfk.207.2017.05.28.07.41.25; Sun, 28 May 2017 07:41:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751109AbdE1OlU (ORCPT + 25 others); Sun, 28 May 2017 10:41:20 -0400 Received: from foss.arm.com ([217.140.101.70]:42136 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751022AbdE1OlR (ORCPT ); Sun, 28 May 2017 10:41:17 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 706BE344; Sun, 28 May 2017 07:41:17 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A55E33F52A; Sun, 28 May 2017 07:41:15 -0700 (PDT) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org Subject: [PATCH 06/12] staging: ccree: move request_mgr to generic bitfield ops Date: Sun, 28 May 2017 17:40:31 +0300 Message-Id: <1495982440-10047-7-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1495982440-10047-1-git-send-email-gilad@benyossef.com> References: <1495982440-10047-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org request_mgr was using custom bit field macros. move over to standard kernel bitfield ops. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/cc_regs.h | 5 +++++ drivers/staging/ccree/ssi_request_mgr.c | 19 +++++++++---------- 2 files changed, 14 insertions(+), 10 deletions(-) -- 2.1.4 diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h index 8b89f06..244bbae 100644 --- a/drivers/staging/ccree/cc_regs.h +++ b/drivers/staging/ccree/cc_regs.h @@ -25,6 +25,11 @@ #include "cc_bitops.h" +#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP) +#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \ + DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \ + DX_AXIM_MON_COMP_VALUE_BIT_SHIFT) + /* Register Offset macro */ #define CC_REG_OFFSET(unit_name, reg_name) \ (DX_BASE_ ## unit_name + DX_ ## reg_name ## _REG_OFFSET) diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c index 683140a..453d731 100644 --- a/drivers/staging/ccree/ssi_request_mgr.c +++ b/drivers/staging/ccree/ssi_request_mgr.c @@ -35,8 +35,6 @@ #define SSI_MAX_POLL_ITER 10 -#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP) - struct ssi_request_mgr_handle { /* Request manager resources */ unsigned int hw_queue_size; /* HW capability */ @@ -516,24 +514,25 @@ static void comp_handler(unsigned long devarg) CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK); /* Avoid race with above clear: Test completion counter once more */ - request_mgr_handle->axi_completed += CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE, - CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); + request_mgr_handle->axi_completed += + FIELD_GET(AXIM_MON_COMP_VALUE, + CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); while (request_mgr_handle->axi_completed) { do { proc_completions(drvdata); - /* At this point (after proc_completions()), request_mgr_handle->axi_completed is always 0. - The following assignment was changed to = (previously was +=) to conform KW restrictions. */ - request_mgr_handle->axi_completed = CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE, - CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); + request_mgr_handle->axi_completed = + FIELD_GET(AXIM_MON_COMP_VALUE, + CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); } while (request_mgr_handle->axi_completed > 0); /* To avoid the interrupt from firing as we unmask it, we clear it now */ CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK); /* Avoid race with above clear: Test completion counter once more */ - request_mgr_handle->axi_completed += CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE, - CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); + request_mgr_handle->axi_completed += + FIELD_GET(AXIM_MON_COMP_VALUE, + CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); } }