From patchwork Wed May 24 10:16:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 100434 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp201800qge; Wed, 24 May 2017 03:17:29 -0700 (PDT) X-Received: by 10.84.228.207 with SMTP id y15mr42055167pli.172.1495621049093; Wed, 24 May 2017 03:17:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495621049; cv=none; d=google.com; s=arc-20160816; b=ym2V+xZiMmSy1EQLeTXWc+eKDwxrbWN1+0Ruc110/sby8nZuFSzbZk55GNxsCXxEoG P6sFNpPBcFwWy5aVuWts48X0Nc7hwEiDJCNSwhtMBenU5Glb6yq35X7QzlO5vTHDo6ww M/e7F9U4aLypIq3sRWbGZQKvnJe10rm5i+qwNLTfjbVTPLteeoXogWL20JBmE+9atkot vm14iJdDfkAuVDR1pkJovXUP8nFPqKuMhCqeiqlJ5Lu260EEPFJegaGFTJIB8C2M7OFF IIJXdAPFvszoJs2xxgAJdjYeL0JjKSMZA21zbk33Gb6n0TyFaR6utvPLoKN6WeTJqAlz wyrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=aRctA3hsoA9rAqDwLbX7p+GpMOxNbEetCrSgKUFTirg=; b=LoDV+U0O7jBV7laSGwkKhzJF87sl3p8CNq1RwASI1Iej65rGew69kOK+H9zAVKJwzY SIBAGdWCXrun9iUvY2MEO+3JrGtw6P0oHNnqaz0fRfMfRwDT8KWKmIsBBSvRHpfHJscq nilqNVh6xMsEQr72pTuYw9rDzFUNYAzW6IywPZcR3/lEV0bhLn0FFpL+HmOVYxsVI1Rk HIK6o6nWmAOL3jz3T0mbTX/tz8wFokg2GBqtl64NiNOcAD/475GVKhGKb5kVrHChUSzr T+21Bq1uk9TMy//NNX2WM5uAFOmYcu0r3xnh6Z3zlzr1sj3INvivwN7sKEtRSvEsmWx0 W9/A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f86si23752824pfj.267.2017.05.24.03.17.28; Wed, 24 May 2017 03:17:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S969292AbdEXKRP (ORCPT + 25 others); Wed, 24 May 2017 06:17:15 -0400 Received: from foss.arm.com ([217.140.101.70]:35522 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936297AbdEXKRC (ORCPT ); Wed, 24 May 2017 06:17:02 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DA1D315BF; Wed, 24 May 2017 03:17:01 -0700 (PDT) Received: from e107155-lin.cambridge.arm.com (unknown [10.1.211.34]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A04783F578; Wed, 24 May 2017 03:17:00 -0700 (PDT) From: Sudeep Holla To: linux-kernel@vger.kernel.org, Jassi Brar Cc: Sudeep Holla , devicetree@vger.kernel.org, Alexey Klimov , Jassi Brar , Rob Herring Subject: [PATCH v2 2/6] Documentation: devicetree: add bindings to support ARM MHU doorbells Date: Wed, 24 May 2017 11:16:39 +0100 Message-Id: <1495621003-4291-3-git-send-email-sudeep.holla@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495621003-4291-1-git-send-email-sudeep.holla@arm.com> References: <1495621003-4291-1-git-send-email-sudeep.holla@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ARM MHU has mechanism to assert interrupt signals to facilitate inter-processor message based communication. It drives the signal using a 32-bit register, with all 32-bits logically ORed together. It also enables software to set, clear and check the status of each of the bits of this register independently. Each bit of the register can be associated with a type of event that can contribute to raising the interrupt thereby allowing it to be used as independent doorbells. Since the first version of this binding can't support doorbells, this patch extends the existing binding to support them. Cc: Alexey Klimov Cc: Jassi Brar Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Sudeep Holla --- .../devicetree/bindings/mailbox/arm-mhu.txt | 46 ++++++++++++++++++++-- 1 file changed, 43 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt index 4971f03f0b33..bd9a3a267caf 100644 --- a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt +++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt @@ -10,21 +10,42 @@ STAT register and the remote clears it after having read the data. The last channel is specified to be a 'Secure' resource, hence can't be used by Linux running NS. +The MHU drives the interrupt signal using a 32-bit register, with all +32-bits logically ORed together. It provides a set of registers to +enable software to set, clear and check the status of each of the bits +of this register independently. The use of 32 bits per interrupt line +enables software to provide more information about the source of the +interrupt. For example, each bit of the register can be associated with +a type of event that can contribute to raising the interrupt. Each of +the 32-bits can be used as "doorbell" to alert the remote processor. + Mailbox Device Node: ==================== Required properties: -------------------- -- compatible: Shall be "arm,mhu" & "arm,primecell" +- compatible: Shall be "arm,primecell" and one of the below: + "arm,mhu" - if the controller doesn't support + doorbell model + "arm,mhu-doorbell" - if the controller supports + doorbell model - reg: Contains the mailbox register address range (base address and length) -- #mbox-cells Shall be 1 - the index of the channel needed. +- #mbox-cells Shall be 1 - the index of the channel needed when + compatible is "arm,mhu" + Shall be 2 - the index of the channel needed, and + the index of the doorbell bit with the channel when + compatible is "arm,mhu-doorbell" - interrupts: Contains the interrupt information corresponding to - each of the 3 links of MHU. + each of the 3 physical channels of MHU namely low + priority non-secure, high priority non-secure and + secure channels. Example: -------- +1. Controller which doesn't support doorbells + mhu: mailbox@2b1f0000 { #mbox-cells = <1>; compatible = "arm,mhu", "arm,primecell"; @@ -41,3 +62,22 @@ used by Linux running NS. reg = <0 0x2e000000 0x4000>; mboxes = <&mhu 1>; /* HP-NonSecure */ }; + +2. Controller which supports doorbells + + mhu: mailbox@2b1f0000 { + #mbox-cells = <2>; + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0 0x2b1f0000 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>, /* HP-NonSecure */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + mhu_client: scb@2e000000 { + compatible = "arm,scpi"; + reg = <0 0x2e000000 0x200>; + mboxes = <&mhu 1 4>; /* HP-NonSecure 5th doorbell bit */ + };