From patchwork Mon May 22 12:48:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 100290 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp1367200obb; Mon, 22 May 2017 05:17:53 -0700 (PDT) X-Received: by 10.84.218.142 with SMTP id r14mr28029883pli.69.1495455473907; Mon, 22 May 2017 05:17:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495455473; cv=none; d=google.com; s=arc-20160816; b=ONwTaL0Cj+qGoiJdJPqkbqB2DRtp0pXMJux78zND8VwlXBle+BbQ2QeUCbUEgGHfVP skL49VeeysSSZUVdcusz2WYz9irpuOdvXm0UdfziMRV6XPDBhb82gCAQsZoJbcqnmKNN hYeL327motFdgHUikjFZuXrEMoSDb1UVpLJsS1xCckw6A6A98LbywJylRkBWCuZtbim7 aDzWo96zMrphhtvQ9pZG4zZqB5/9jWJTEpV+lO0pFhlvlwOATmifHGobkU2/Zoc66h6V cOPemm7U+X5gDLxr+YCNnaLanpNmIJdk1DY42kPJ9nXLo7+8ATXQMBcbEO/qLpUZoy9H kQsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=biDvJHoNmmaOs66rEa5ggXj1RKi0NitJYvuYABLJk3o=; b=V+WkfZZTrp57aZSPJ+zF3EwUPxDSsT2WfDkMuf+svOVQs4oWE5sa/Gw+eJ9c6PYfCJ 7XnWP+6R9MNBgoyX4JbW3kJg+XpRrYIbF+fkeF007ZQiduwW78Ceg+ZYNPLxdqCiWEAT YqQWJwGHpSRGFOkY9CAFoJq3II25cc8wh5eQEYAsHlReEumVk1x5Txb+WXnaF1u3dtYy Jb/F02swBZUBou9MYpUzAo3ETON1HoLCvQFS5di4r0p54XPzfOs+6UV1gWeLeL1DxAl5 1ssiw3lsTDalg93jDdAtKEj9k5wTV89EP+YGphRBrZIQVufNvRLkr3VpfeF31qDnJlGI CLFA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f13si17222149pga.4.2017.05.22.05.17.53; Mon, 22 May 2017 05:17:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759302AbdEVMRh (ORCPT + 25 others); Mon, 22 May 2017 08:17:37 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6368 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757890AbdEVMRd (ORCPT ); Mon, 22 May 2017 08:17:33 -0400 Received: from 172.30.72.54 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.54]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOA30821; Mon, 22 May 2017 20:17:26 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Mon, 22 May 2017 20:17:19 +0800 From: Shaokun Zhang To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v8 5/9] drivers: perf: hisi: Update Kconfig for Hisilicon PMU support Date: Mon, 22 May 2017 20:48:29 +0800 Message-ID: <1495457309-236380-1-git-send-email-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.5922D6D6.00CE, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ec912be545986dfd23e047010d2b7d03 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anurup M Update Kconfig for HiP05/06/07 PMU support. Signed-off-by: Anurup M Signed-off-by: Shaokun Zhang Signed-off-by: John Garry --- drivers/perf/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) -- 1.9.1 diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index aa587ed..4bc1f09 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -16,6 +16,14 @@ config ARM_PMU_ACPI depends on ARM_PMU && ACPI def_bool y +config HISI_PMU + bool "HiSilicon SoC PMU" + depends on PERF_EVENTS && ARM64 + help + Enable hardware event counter support for hardware event counters + in Hisilicon HiP05/06/07 SoC. The hardware modules like L3 Cache + and MN have hardware events and counters. + config QCOM_L2_PMU bool "Qualcomm Technologies L2-cache PMU" depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI