From patchwork Sun Apr 16 20:26:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 97485 Delivered-To: patch@linaro.org Received: by 10.140.109.52 with SMTP id k49csp1087799qgf; Sun, 16 Apr 2017 13:32:50 -0700 (PDT) X-Received: by 10.98.81.132 with SMTP id f126mr7277718pfb.95.1492374770442; Sun, 16 Apr 2017 13:32:50 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b69si8929614pfl.158.2017.04.16.13.32.50; Sun, 16 Apr 2017 13:32:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756863AbdDPU2O (ORCPT + 15 others); Sun, 16 Apr 2017 16:28:14 -0400 Received: from mail-wm0-f51.google.com ([74.125.82.51]:38520 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756749AbdDPU2H (ORCPT ); Sun, 16 Apr 2017 16:28:07 -0400 Received: by mail-wm0-f51.google.com with SMTP id t189so22462791wmt.1 for ; Sun, 16 Apr 2017 13:28:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TQk8Kgb0zx9O9j0tJWE4t6Rvdaf2oTmFTagZJxH+f3w=; b=Mm4P8M8HW0nQjg8GnP7zHKD9nZvD2ECQzpghMJ5arGpK72THvvoBMtw4u2/F401bst 0uKzGnnq8y50yd6rPix9QO/1dDk0jmr7yW25CfqgxZP7PSEKhlTQlR0Fu7y39GLG1rzZ LfkoNBuExiuoPSJneuzkC93s6lbsuhCLMMDxM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TQk8Kgb0zx9O9j0tJWE4t6Rvdaf2oTmFTagZJxH+f3w=; b=bNNbfGqMscDhVW/3KW0lHwyDiqfo0MPxRros69cudf0ykbpIQPyK6+bj4OSx2Yeft8 R7aDD0lDqB5K0JaW0kusDUtDZ/74wHlJwbUPsJXuwVvib9f4uYDGsNrSMHUn5a/fJxur J152hvcKInFOrOJjwXQLYs373U4VZM91636KAWP1z76iOtCCj+OhnJ+HDBuausq04XHZ A2PMbihoBQwkjBOa+18DPYKcWa/Lmz89jKq4ioCrOOw5Kuloc5jDpwtt+M07zpLiC0nS BC3ktD6/ET71hNDAi21bS45XhH3UvCozn1s6hz0gEdS+9enhEWbBxLY259awR1/5lnra ZY/g== X-Gm-Message-State: AN3rC/67nCQldbbUDxUW5PxRoLXLrxsL+3J6yd2ow8YMdz9zMXLJqseO On1EGvzL+vZYtbp0Qx5jiA== X-Received: by 10.28.111.134 with SMTP id c6mr6292024wmi.128.1492374481197; Sun, 16 Apr 2017 13:28:01 -0700 (PDT) Received: from mai.lan ([2001:41d0:fe90:b800:20c0:6248:a385:db35]) by smtp.gmail.com with ESMTPSA id 81sm7732196wmj.9.2017.04.16.13.27.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 16 Apr 2017 13:28:00 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Marc Zyngier , Catalin Marinas , Will Deacon , Jonathan Corbet , Christopher Covington , Suzuki K Poulose , Andre Przywara , Robert Richter , James Morse , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-doc@vger.kernel.org (open list:DOCUMENTATION) Subject: [PATCH 05/29] arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 Date: Sun, 16 Apr 2017 22:26:55 +0200 Message-Id: <1492374441-23336-5-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> References: <20170416202542.GV2078@mai> <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier In order to work around Cortex-A73 erratum 858921 in a subsequent patch, add the required capability that advertise the erratum. As the configuration option it depends on is not present yet, this has no immediate effect. Acked-by: Thomas Gleixner Acked-by: Daniel Lezcano Signed-off-by: Marc Zyngier --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/kernel/cpu_errata.c | 8 ++++++++ 3 files changed, 11 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 2f66683..10f2ddd 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -54,6 +54,7 @@ stable kernels. | ARM | Cortex-A57 | #852523 | N/A | | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | | ARM | Cortex-A72 | #853709 | N/A | +| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | | ARM | MMU-500 | #841119,#826419 | N/A | | | | | | | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index fb78a5d..b3aab8a 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -37,7 +37,8 @@ #define ARM64_HAS_NO_FPSIMD 16 #define ARM64_WORKAROUND_REPEAT_TLBI 17 #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18 +#define ARM64_WORKAROUND_858921 19 -#define ARM64_NCAPS 19 +#define ARM64_NCAPS 20 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 2be1d1c..2ed2a76 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -158,6 +158,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_CPU_VAR_REV(0, 0)), }, #endif +#ifdef CONFIG_ARM64_ERRATUM_858921 + { + /* Cortex-A73 all versions */ + .desc = "ARM erratum 858921", + .capability = ARM64_WORKAROUND_858921, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + }, +#endif { } };