From patchwork Sun Apr 16 20:26:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 97487 Delivered-To: patch@linaro.org Received: by 10.182.246.10 with SMTP id xs10csp1090553obc; Sun, 16 Apr 2017 13:33:23 -0700 (PDT) X-Received: by 10.98.137.221 with SMTP id n90mr8500737pfk.52.1492374803040; Sun, 16 Apr 2017 13:33:23 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b69si8929614pfl.158.2017.04.16.13.33.22; Sun, 16 Apr 2017 13:33:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756809AbdDPU14 (ORCPT + 15 others); Sun, 16 Apr 2017 16:27:56 -0400 Received: from mail-wr0-f178.google.com ([209.85.128.178]:33883 "EHLO mail-wr0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751900AbdDPU1w (ORCPT ); Sun, 16 Apr 2017 16:27:52 -0400 Received: by mail-wr0-f178.google.com with SMTP id z109so74465979wrb.1 for ; Sun, 16 Apr 2017 13:27:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N+enDjm3vtLxViYvZCoKczu8VzRCgY1O8okTucTvpEs=; b=DlwXIxrcpZXlpzYpLysKVVur9wnGeM1bpEuJWgA93tfTUfftgyR1nx3ooQaNilTVMr FClZ8wNWeo5kJ/gN+Xd+43vtKAuZ/o3KVSbUiNbvyEZPAk88I09vUWrtWL2nyiPEbtnk NQcIyRLbKvvE+5nfiRSVVp6aF2WJ4fp4lQ2Qk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N+enDjm3vtLxViYvZCoKczu8VzRCgY1O8okTucTvpEs=; b=e0P5ZRonf9v9rq6RjVkICeBxn4wVpHVqgXH6Y1FxaLOXHqKq2nAr+YPk9teF/QZ5UO gO4LyRqhlQOaRgNYMOsMmGMZOfI0zA5iGn7rE1Gp/91ICtV9AN3qJtC9+lPHRkgs96Vu TpTINAwPmdioidAuvU2kGFy2zO2F5aXh/u9e0sZbrhjsl/NTwzeSXkQ45IEFhHs69LM2 DaC0gB37alBugX8xY2lpQp2UPU/nSzEG/6s6OKe65TlLyx2BjlvM59qrqJkaLw31Osy3 H2S3gCl8DzzWy5V4Xi1fH4fvLfLgw+zaTFaDp6q1vj7fVzRmrIvHcxS0nHDcmRdLrNGJ +b2A== X-Gm-Message-State: AN3rC/7tocXdO7YdpvXrN+yzP3Xc6YsnvAFxqlUT/WkDHF90zcIjBXHA yrwqL6+yZZqGhc0g X-Received: by 10.223.165.130 with SMTP id g2mr14562502wrc.183.1492374470743; Sun, 16 Apr 2017 13:27:50 -0700 (PDT) Received: from mai.lan ([2001:41d0:fe90:b800:20c0:6248:a385:db35]) by smtp.gmail.com with ESMTPSA id 81sm7732196wmj.9.2017.04.16.13.27.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 16 Apr 2017 13:27:50 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Marc Zyngier , Mark Rutland , Catalin Marinas , Will Deacon , Christopher Covington , Shanker Donthineni , Ganapatrao Kulkarni , Robert Richter , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)) Subject: [PATCH 03/29] arm64: Define Cortex-A73 MIDR Date: Sun, 16 Apr 2017 22:26:53 +0200 Message-Id: <1492374441-23336-3-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> References: <20170416202542.GV2078@mai> <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier As we're about to introduce a new workaround that is specific to Cortex-A73, let's define the coresponding MIDR. Acked-by: Thomas Gleixner Acked-by: Mark Rutland Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) -- 2.7.4 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index fc50271..0984d1b 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -80,6 +80,7 @@ #define ARM_CPU_PART_FOUNDATION 0xD00 #define ARM_CPU_PART_CORTEX_A57 0xD07 #define ARM_CPU_PART_CORTEX_A53 0xD03 +#define ARM_CPU_PART_CORTEX_A73 0xD09 #define APM_CPU_PART_POTENZA 0x000 @@ -92,6 +93,7 @@ #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) +#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)