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[03/29] arm64: Define Cortex-A73 MIDR

Message ID	1492374441-23336-3-git-send-email-daniel.lezcano@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; From: Daniel Lezcano <daniel.lezcano@linaro.org> To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Marc Zyngier <marc.zyngier@arm.com>, Mark Rutland <mark.rutland@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Christopher Covington <cov@codeaurora.org>, Shanker Donthineni <shankerd@codeaurora.org>, Ganapatrao Kulkarni <gkulkarni@caviumnetworks.com>, Robert Richter <rrichter@cavium.com>, linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)) Subject: [PATCH 03/29] arm64: Define Cortex-A73 MIDR Date: Sun, 16 Apr 2017 22:26:53 +0200 Message-Id: <1492374441-23336-3-git-send-email-daniel.lezcano@linaro.org> In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> References: <20170416202542.GV2078@mai> <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk
Series	[01/29] arm64: Allow checking of a CPU-local erratum \| expand [01/29] arm64: Allow checking of a CPU-local erratum [02/29] arm64: Add CNTVCT_EL0 trap handler [03/29] arm64: Define Cortex-A73 MIDR [04/29] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core [05/29] arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 [06/29] arm64: arch_timer: Add infrastructure for multiple erratum detection methods [07/29] arm64: arch_timer: Add erratum handler for CPU-specific capability [08/29] arm64: arch_timer: Move arch_timer_reg_read/write around [09/29] arm64: arch_timer: Get rid of erratum_workaround_set_sne [10/29] arm64: arch_timer: Rework the set_next_event workarounds [11/29] arm64: arch_timer: Make workaround methods optional [12/29] arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs [13/29] arm64: arch_timer: Move clocksource_counter and co around [14/29] arm64: arch_timer: Save cntkctl_el1 as a per-cpu variable [15/29] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled [16/29] arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 [17/29] arm64: arch_timer: Allow erratum matching with ACPI OEM information [18/29] arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data [19/29] clocksource/drivers/orion: Read clock rate once [20/29] clocksource/drivers/orion: Add delay_timer implementation [21/29] clocksource: Add missing line break to error messages [22/29] dt-bindings: Clarify compatible property for rockchip timers [23/29] ARM: dts: rockchip: Update compatible property for rk322x timer [24/29] clocksource/drivers/rockchip_timer: Implement clocksource timer [25/29] ARM: dts: rockchip: Add timer entries to rk3188 SoC [27/29] clocksource: Augment bindings for Faraday timer [28/29] clocksource/drivers/gemini: Rename Gemini timer to Faraday [29/29] clocksource/drivers/fttmr010: Refactor to handle clock

Commit Message

Daniel Lezcano April 16, 2017, 8:26 p.m. UTC

From: Marc Zyngier <marc.zyngier@arm.com>


As we're about to introduce a new workaround that is specific to
Cortex-A73, let's define the coresponding MIDR.

Acked-by: Thomas Gleixner <tglx@linutronix.de>

Acked-by: Mark Rutland <mark.rutland@arm.com>

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

---
 arch/arm64/include/asm/cputype.h | 2 ++
 1 file changed, 2 insertions(+)

-- 
2.7.4

diff mbox series

Patch

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index fc50271..0984d1b 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -80,6 +80,7 @@ 
 #define ARM_CPU_PART_FOUNDATION		0xD00
 #define ARM_CPU_PART_CORTEX_A57		0xD07
 #define ARM_CPU_PART_CORTEX_A53		0xD03
+#define ARM_CPU_PART_CORTEX_A73		0xD09
 
 #define APM_CPU_PART_POTENZA		0x000
 
@@ -92,6 +93,7 @@ 
 
 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
+#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)