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[209.132.180.67]) by mx.google.com with ESMTP id f62si1461208pfg.96.2017.04.16.13.30.32; Sun, 16 Apr 2017 13:30:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757226AbdDPUaQ (ORCPT + 15 others); Sun, 16 Apr 2017 16:30:16 -0400 Received: from mail-wm0-f45.google.com ([74.125.82.45]:37160 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757115AbdDPU3D (ORCPT ); Sun, 16 Apr 2017 16:29:03 -0400 Received: by mail-wm0-f45.google.com with SMTP id u2so22409511wmu.0 for ; Sun, 16 Apr 2017 13:28:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Dle/NQY282WKPJYupLtRcMj3rM9bSvkdbgQeOrhHrFA=; b=ZZFaoxI5rhtR7y5xAWzTNYw9TfrEctnUCQNHhikyPqsIamdnGaop5qG/wrjkJTNbfL nSB1NLoYVG6lYd8xnjgA1/tT6NzkAw+iJpmuwKfGBdI53VKQwbkyG4q6aZHmcIAR3EmX 1DEtWC23BlP+CDJ61+Cg/MumQ/MBij3Z5vSK4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Dle/NQY282WKPJYupLtRcMj3rM9bSvkdbgQeOrhHrFA=; b=cIwEej1WJWXToztCRwrGCLP/dt4PlrXpV9MVXDsPQaX875+PjeOIpN+7pZPDoGR0De tV6QGKoJYJ671h4BHvo7K0eBWoHjGhboJtAP4erAGQp+3HA5TdkHf3XHHuN6cL0s5AW7 sz61/8+rO2xbtOG6OHFMcwmyMlRe7bsf7db7/otJ2sndToIriKwIsy4lTDhw2zPVwStL ubgusyUVO4zryo+IyW6B+6mBZua5f9EogjRh05ifehRQCUpLu8YYQxa6UwBf3QJpmPjQ dRtrmefcZ6MJf5KFjVX/UlGzDr7N7+pY4V2Tq1LFwnFnQw6S4aXnicePi2uxA311cb8Z /53A== X-Gm-Message-State: AN3rC/7XiPIpojorXvrVYBEuzGLD44fe/J1uTgDdQtKkQqlSqEG7ykQJ 1g3XWLI4ZYoPwpu/ X-Received: by 10.28.139.1 with SMTP id n1mr4983680wmd.132.1492374527482; Sun, 16 Apr 2017 13:28:47 -0700 (PDT) Received: from mai.lan ([2001:41d0:fe90:b800:20c0:6248:a385:db35]) by smtp.gmail.com with ESMTPSA id 81sm7732196wmj.9.2017.04.16.13.28.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 16 Apr 2017 13:28:46 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Alexander Kochetkov , Heiko Stuebner , Rob Herring , Mark Rutland , Russell King , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 25/29] ARM: dts: rockchip: Add timer entries to rk3188 SoC Date: Sun, 16 Apr 2017 22:27:15 +0200 Message-Id: <1492374441-23336-25-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> References: <20170416202542.GV2078@mai> <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexander Kochetkov The patch add two timers to all rk3188 based boards. The first timer is from alive subsystem and it act as a backup for the local timers at sleep time. It act the same as other SoC rockchip timers already present in kernel. The second timer is from CPU subsystem and act as replacement for the arm-global-timer clocksource and sched clock. It run at stable frequency 24MHz. Signed-off-by: Alexander Kochetkov Signed-off-by: Daniel Lezcano Reviewed-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.7.4 diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index cf91254..8428fae 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -106,6 +106,22 @@ }; }; + timer3: timer@2000e000 { + compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; + reg = <0x2000e000 0x20>; + interrupts = ; + clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>; + clock-names = "timer", "pclk"; + }; + + timer6: timer@200380a0 { + compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; + reg = <0x200380a0 0x20>; + interrupts = ; + clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + }; + i2s0: i2s@1011a000 { compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; reg = <0x1011a000 0x2000>;