From patchwork Sun Apr 16 20:26:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 97490 Delivered-To: patch@linaro.org Received: by 10.182.246.10 with SMTP id xs10csp1090661obc; Sun, 16 Apr 2017 13:34:06 -0700 (PDT) X-Received: by 10.84.248.74 with SMTP id e10mr11420066pln.76.1492374846322; Sun, 16 Apr 2017 13:34:06 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u17si3535785plj.273.2017.04.16.13.34.06; Sun, 16 Apr 2017 13:34:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757123AbdDPUd7 (ORCPT + 15 others); Sun, 16 Apr 2017 16:33:59 -0400 Received: from mail-wm0-f46.google.com ([74.125.82.46]:36240 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756774AbdDPU1s (ORCPT ); Sun, 16 Apr 2017 16:27:48 -0400 Received: by mail-wm0-f46.google.com with SMTP id o81so23408135wmb.1 for ; Sun, 16 Apr 2017 13:27:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oSzs1ENVwHUuAuYFfwWNV0WdGDMKqPb89xXnduz/x6c=; b=iFcSgbJ5aM/hfRxD96f/A3VHTqB05HduYAB+t7aqa/YqNHDlmM188zFMpnfpeH9pLA 9iXQ5wJl2h0Q3nBlMVpuYejub2Ms4c5b1Z9b+MUmL2Yxfh7XU6Vrx9O04Y17tI3YgmDm k27wXqiwDPbHBm4+uHIOqWvT9bh4gWEbz5ov4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oSzs1ENVwHUuAuYFfwWNV0WdGDMKqPb89xXnduz/x6c=; b=pIqxGRbkVLUftT1K6yobb06IgGfhfXT+xllqIwEcQbKw+VuNfjqWC63FMeZb7YlMjk dpHm/wOtcbrDHoL38GeD82SZWF63dWxJVauPn5XNyHX1kXbWAKE29i3CqdDwEDTX9S4r IEGijVk3x0Z05ffbpsTc0JtMUkQTmQJW7S29QIQ8xq0v6SvKM8M5qhyP/q6FLf8sA4ME JmRpgOumVlU2GRsO+bsVxFheuANEN0EzHwBVbZecz1SnNYuzpiMtRCqhXrAe4yVpaNcQ Szw9MUESO0gSwHtfbi4rN0R885MxzLG4tmb4knt2fohkwbqHKRi68hKLLd8gLUe9WlzT cO1A== X-Gm-Message-State: AN3rC/7emenU9nxS188/DNXzeuTLijEbq0+zGU9cwPqBi/cRkJKWEfM5 f2UU3c1F6ruaVfaa X-Received: by 10.28.140.17 with SMTP id o17mr6016833wmd.14.1492374467510; Sun, 16 Apr 2017 13:27:47 -0700 (PDT) Received: from mai.lan ([2001:41d0:fe90:b800:20c0:6248:a385:db35]) by smtp.gmail.com with ESMTPSA id 81sm7732196wmj.9.2017.04.16.13.27.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 16 Apr 2017 13:27:47 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Marc Zyngier , Mark Rutland , Catalin Marinas , Will Deacon , Suzuki K Poulose , Andre Przywara , Ingo Molnar , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)) Subject: [PATCH 02/29] arm64: Add CNTVCT_EL0 trap handler Date: Sun, 16 Apr 2017 22:26:52 +0200 Message-Id: <1492374441-23336-2-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> References: <20170416202542.GV2078@mai> <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier Since people seem to make a point in breaking the userspace visible counter, we have no choice but to trap the access. Add the required handler. Acked-by: Thomas Gleixner Acked-by: Mark Rutland Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/esr.h | 2 ++ arch/arm64/kernel/traps.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) -- 2.7.4 diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index d14c478..ad42e79 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -175,6 +175,8 @@ #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ ESR_ELx_SYS64_ISS_DIR_READ) +#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ + ESR_ELx_SYS64_ISS_DIR_READ) #ifndef __ASSEMBLY__ #include diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index e52be6a..1de444e 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -505,6 +505,14 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) regs->pc += 4; } +static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) +{ + int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; + + pt_regs_write_reg(regs, rt, arch_counter_get_cntvct()); + regs->pc += 4; +} + struct sys64_hook { unsigned int esr_mask; unsigned int esr_val; @@ -523,6 +531,12 @@ static struct sys64_hook sys64_hooks[] = { .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, .handler = ctr_read_handler, }, + { + /* Trap read access to CNTVCT_EL0 */ + .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, + .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, + .handler = cntvct_read_handler, + }, {}, };