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[209.132.180.67]) by mx.google.com with ESMTP id p127si1326720pfg.319.2017.04.16.13.31.40; Sun, 16 Apr 2017 13:31:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757243AbdDPUbg (ORCPT + 15 others); Sun, 16 Apr 2017 16:31:36 -0400 Received: from mail-wr0-f177.google.com ([209.85.128.177]:33953 "EHLO mail-wr0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756988AbdDPU2f (ORCPT ); Sun, 16 Apr 2017 16:28:35 -0400 Received: by mail-wr0-f177.google.com with SMTP id z109so74470075wrb.1 for ; Sun, 16 Apr 2017 13:28:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fqTbnqWLjd0jRvyjfFMXBPMmg8YO29nzqxzblYAu3Yw=; b=j7ZjDnlhpmfhufxENT2bW0qDbl1obZKFqfd88JraqM0dWSHI6nCkOqbJrvHwkcrik3 fkLPYLiMZPT0PgKIvRCbTVrIS1C7brejrDpWRYt9fcM+K+1aTLjx7G+g595WeOKlzQHj gVX4uYbi+TlTamSjUx1IrJUsms2VuIqM70/Qg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fqTbnqWLjd0jRvyjfFMXBPMmg8YO29nzqxzblYAu3Yw=; b=chY3fLTEs8PQ+598tUfzMipOQt0p85jUPfuM2DExph4goN7TPWaLMSd14txnIdrJ3U WYql7ITeGrH8Jm4R80S5DMoXcky383yPp5jRqvQ6HHpVS5CzziInc6yPUqutrndtax+O 2gBhkeHQVuM1ttBoO1B7PlW7Itgcs6Ch56d726mW9RrTknrcTYiL2cB+3wj1hmHvXy46 VphNe8I6UK81M4csZL/D6lVgzFfOpe1OmNjf65EyvqEltxaXGMPuhAAWhDVT41MUDTaH gktMmeawkMBgoN7x4ZlWIcTKq1aIe5QXGBIN+qKqGuxX/+kNrZvlNNsZsE9yTLRVbN4d yipQ== X-Gm-Message-State: AN3rC/4Z1BkZ+VogGO7uyBMO7BMQT+tKn6ZbG2QAtZp02G3jUNdGKN0R JbU4G3EQ4AXrDrI1SPmT2w== X-Received: by 10.223.152.107 with SMTP id v98mr15031632wrb.60.1492374508797; Sun, 16 Apr 2017 13:28:28 -0700 (PDT) Received: from mai.lan ([2001:41d0:fe90:b800:20c0:6248:a385:db35]) by smtp.gmail.com with ESMTPSA id 81sm7732196wmj.9.2017.04.16.13.28.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 16 Apr 2017 13:28:28 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Russell King Subject: [PATCH 19/29] clocksource/drivers/orion: Read clock rate once Date: Sun, 16 Apr 2017 22:27:09 +0200 Message-Id: <1492374441-23336-19-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> References: <20170416202542.GV2078@mai> <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Russell King Rather than reading the clock rate three times, read it once - we are about to add a fourth usage. Signed-off-by: Russell King Signed-off-by: Daniel Lezcano --- drivers/clocksource/time-orion.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/time-orion.c b/drivers/clocksource/time-orion.c index a28f496..c4818a5 100644 --- a/drivers/clocksource/time-orion.c +++ b/drivers/clocksource/time-orion.c @@ -106,6 +106,7 @@ static struct irqaction orion_clkevt_irq = { static int __init orion_timer_init(struct device_node *np) { + unsigned long rate; struct clk *clk; int irq, ret; @@ -135,6 +136,8 @@ static int __init orion_timer_init(struct device_node *np) return -EINVAL; } + rate = clk_get_rate(clk); + /* setup timer0 as free-running clocksource */ writel(~0, timer_base + TIMER0_VAL); writel(~0, timer_base + TIMER0_RELOAD); @@ -142,15 +145,15 @@ static int __init orion_timer_init(struct device_node *np) TIMER0_RELOAD_EN | TIMER0_EN, TIMER0_RELOAD_EN | TIMER0_EN); - ret = clocksource_mmio_init(timer_base + TIMER0_VAL, "orion_clocksource", - clk_get_rate(clk), 300, 32, + ret = clocksource_mmio_init(timer_base + TIMER0_VAL, + "orion_clocksource", rate, 300, 32, clocksource_mmio_readl_down); if (ret) { pr_err("Failed to initialize mmio timer"); return ret; } - sched_clock_register(orion_read_sched_clock, 32, clk_get_rate(clk)); + sched_clock_register(orion_read_sched_clock, 32, rate); /* setup timer1 as clockevent timer */ ret = setup_irq(irq, &orion_clkevt_irq); @@ -162,7 +165,7 @@ static int __init orion_timer_init(struct device_node *np) ticks_per_jiffy = (clk_get_rate(clk) + HZ/2) / HZ; orion_clkevt.cpumask = cpumask_of(0); orion_clkevt.irq = irq; - clockevents_config_and_register(&orion_clkevt, clk_get_rate(clk), + clockevents_config_and_register(&orion_clkevt, rate, ORION_ONESHOT_MIN, ORION_ONESHOT_MAX); return 0;