From patchwork Sun Apr 16 20:27:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 97471 Delivered-To: patch@linaro.org Received: by 10.140.109.52 with SMTP id k49csp1086966qgf; Sun, 16 Apr 2017 13:29:01 -0700 (PDT) X-Received: by 10.98.97.7 with SMTP id v7mr8200840pfb.161.1492374541068; Sun, 16 Apr 2017 13:29:01 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r75si8917811pfa.171.2017.04.16.13.29.00; Sun, 16 Apr 2017 13:29:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757062AbdDPU2s (ORCPT + 15 others); Sun, 16 Apr 2017 16:28:48 -0400 Received: from mail-wr0-f180.google.com ([209.85.128.180]:35177 "EHLO mail-wr0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756980AbdDPU2d (ORCPT ); Sun, 16 Apr 2017 16:28:33 -0400 Received: by mail-wr0-f180.google.com with SMTP id o21so74478043wrb.2 for ; Sun, 16 Apr 2017 13:28:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rZuk+5g4o6qFmWo5sn0TrqGGVT/whPMA7JMuYEarPzc=; b=Cp2bUPMR1wZZppI9m3h7CXw3fhH1OFXPC3tCMPQKdi+m4ubRbP7zRfVT80eElCMla5 20hIb9maGLIxf9zLp71TihpFQrRiAWBUZn6iVbIOv+IgIRRxwHN/cmaMysdWjvNCObiV wrmXXSyjBN59ZZEZQlnX20Y9DfhkpwlSEvnU0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rZuk+5g4o6qFmWo5sn0TrqGGVT/whPMA7JMuYEarPzc=; b=JfAleNRHjN2QVfi+D3upUviPcVUYDXc22BDPzIzCL7tNdUwnHIyQUm0FeL6y//mHBx euICZzaYiO5IlOfIIWaZlRDtmdPSRgPkydncHgRl1Tkh4L7YHQJ0wWd+DJ59z3E/3paS X/yUz/xMUvgxZ2KlP7wY02SQBx0k4lpt5LdCJKPz2FPjDdQgcxONt4HWC5QUdiFW6bPB kL3fr7obsfJ8Iqlq3FGbEvB8II/jRsgIujRETn7z6DKl4uwhmE1yVHwHuBaHDS8AQ48C lgysC4RHqcZ4IyKbvm675pAcKaLnKHPXXRNYFyYCff6V0K64lSz9j1luCf1Ul0kAEr0o +oRA== X-Gm-Message-State: AN3rC/6levcoqURm2yo69pTj2MKy9wRskL17Az9WaNory7OYJ/70Lm/d JWzpy62gZ4diAY2R X-Received: by 10.223.179.24 with SMTP id j24mr16245535wrd.172.1492374507376; Sun, 16 Apr 2017 13:28:27 -0700 (PDT) Received: from mai.lan ([2001:41d0:fe90:b800:20c0:6248:a385:db35]) by smtp.gmail.com with ESMTPSA id 81sm7732196wmj.9.2017.04.16.13.28.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 16 Apr 2017 13:28:26 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Marc Zyngier , dann frazier , Hanjun Guo , Mark Rutland , linux-arm-kernel@lists.infradead.org (moderated list:ARM ARCHITECTED TIMER DRIVER) Subject: [PATCH 18/29] arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data Date: Sun, 16 Apr 2017 22:27:08 +0200 Message-Id: <1492374441-23336-18-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> References: <20170416202542.GV2078@mai> <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier In order to deal with ACPI enabled platforms suffering from the HISILICON_ERRATUM_161010101, let's add the required OEM data that allow the workaround to be enabled. Acked-by: Thomas Gleixner Tested-by: dann frazier Tested-by: Hanjun Guo Reviewed-by: Hanjun Guo Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 887f6d0..bf9e9d7 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -270,6 +270,29 @@ static u64 notrace hisi_161010101_read_cntvct_el0(void) { return __hisi_161010101_read_reg(cntvct_el0); } + +static struct ate_acpi_oem_info hisi_161010101_oem_info[] = { + /* + * Note that trailing spaces are required to properly match + * the OEM table information. + */ + { + .oem_id = "HISI ", + .oem_table_id = "HIP05 ", + .oem_revision = 0, + }, + { + .oem_id = "HISI ", + .oem_table_id = "HIP06 ", + .oem_revision = 0, + }, + { + .oem_id = "HISI ", + .oem_table_id = "HIP07 ", + .oem_revision = 0, + }, + { /* Sentinel indicating the end of the OEM array */ }, +}; #endif #ifdef CONFIG_ARM64_ERRATUM_858921 @@ -347,6 +370,16 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .set_next_event_phys = erratum_set_next_event_tval_phys, .set_next_event_virt = erratum_set_next_event_tval_virt, }, + { + .match_type = ate_match_acpi_oem_info, + .id = hisi_161010101_oem_info, + .desc = "HiSilicon erratum 161010101", + .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, + .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, + .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, + .set_next_event_phys = erratum_set_next_event_tval_phys, + .set_next_event_virt = erratum_set_next_event_tval_virt, + }, #endif #ifdef CONFIG_ARM64_ERRATUM_858921 {