From patchwork Sun Apr 16 20:27:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 97469 Delivered-To: patch@linaro.org Received: by 10.140.109.52 with SMTP id k49csp1086908qgf; Sun, 16 Apr 2017 13:28:43 -0700 (PDT) X-Received: by 10.84.236.74 with SMTP id h10mr11081996pln.91.1492374523540; Sun, 16 Apr 2017 13:28:43 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r7si8937302ple.25.2017.04.16.13.28.43; Sun, 16 Apr 2017 13:28:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757012AbdDPU2i (ORCPT + 15 others); Sun, 16 Apr 2017 16:28:38 -0400 Received: from mail-wm0-f50.google.com ([74.125.82.50]:37102 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756948AbdDPU22 (ORCPT ); Sun, 16 Apr 2017 16:28:28 -0400 Received: by mail-wm0-f50.google.com with SMTP id u2so22406493wmu.0 for ; Sun, 16 Apr 2017 13:28:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KCqS06x62gfjSoWN/cKQ9JpVGCYeFQgvc6RL6zx9kMY=; b=dOvhudsNCMUaInPFwngos2joawwy1RucyYD2S676cFb0NU3hrKS/KLexZ42KpxfO5O nSbGpQRcPjQJrqepdRW5Whit5YJf/3ifTJ6Ws6idcoZjDwSSzDVm7QCWsyO81vnKE8AN mC0YyJdBCNnD4Nu4uhxovQzvKOE5omvjxR0FE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KCqS06x62gfjSoWN/cKQ9JpVGCYeFQgvc6RL6zx9kMY=; b=J472+QnBz1l47ht9TGeWge2xFAf3QISf5/SzD8ou8/TW689IxeqDFhNRFEBC6RwSDS otl1CQhZ0V/2RREqUfPiXOR7oA1KUVOXpeQCXQdOjGGZc5iuYlQ55ZKQdwengfMskT9g /L4JsZvmVdlxVp3nS23o+2O+8wFbyWh4q7p74LSzf+i3cB5NP+cXvDlKINa74zs92e8o Q+LA2DYdzR27gNhyyN0UV86PO8IyhlTMeo0MTetWllbyF5tsahhqjcZ/oV7TTyPWjFXd nMozJXKC4qFTOaM7dmOXB/10Kk7f9teHHc6jdDmC4ZWeRIiO3xqSbC3rtxwDWDZ9zA6V GnpQ== X-Gm-Message-State: AN3rC/4Lo8zNgtDgoZ0ZR4Mp67Oy/9UxxsqS96y+QYo1Arz7WKuvy4uY S0CCWNOzU7OTcN9j X-Received: by 10.28.107.13 with SMTP id g13mr6363367wmc.117.1492374501853; Sun, 16 Apr 2017 13:28:21 -0700 (PDT) Received: from mai.lan ([2001:41d0:fe90:b800:20c0:6248:a385:db35]) by smtp.gmail.com with ESMTPSA id 81sm7732196wmj.9.2017.04.16.13.28.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 16 Apr 2017 13:28:21 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Marc Zyngier , Mark Rutland , linux-arm-kernel@lists.infradead.org (moderated list:ARM ARCHITECTED TIMER DRIVER) Subject: [PATCH 16/29] arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 Date: Sun, 16 Apr 2017 22:27:06 +0200 Message-Id: <1492374441-23336-16-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> References: <20170416202542.GV2078@mai> <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier Cortex-A73 (all versions) counter read can return a wrong value when the counter crosses a 32bit boundary. The workaround involves performing the read twice, and to return one or the other depending on whether a transition has taken place. Acked-by: Thomas Gleixner Signed-off-by: Marc Zyngier --- drivers/clocksource/Kconfig | 11 +++++++++++ drivers/clocksource/arm_arch_timer.c | 19 +++++++++++++++++++ 2 files changed, 30 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 3356ab8..af80a7c 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -366,6 +366,17 @@ config HISILICON_ERRATUM_161010101 161010101. The workaround will be active if the hisilicon,erratum-161010101 property is found in the timer node. +config ARM64_ERRATUM_858921 + bool "Workaround for Cortex-A73 erratum 858921" + default y + select ARM_ARCH_TIMER_OOL_WORKAROUND + depends on ARM_ARCH_TIMER && ARM64 + help + This option enables a workaround applicable to Cortex-A73 + (all versions), whose counter may return incorrect values. + The workaround will be dynamically enabled when an affected + core is detected. + config ARM_GLOBAL_TIMER bool "Support for the ARM global timer" if COMPILE_TEST select CLKSRC_OF if OF diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index f8adea2..8459d19 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -266,6 +266,17 @@ static u64 notrace hisi_161010101_read_cntvct_el0(void) } #endif +#ifdef CONFIG_ARM64_ERRATUM_858921 +static u64 notrace arm64_858921_read_cntvct_el0(void) +{ + u64 old, new; + + old = read_sysreg(cntvct_el0); + new = read_sysreg(cntvct_el0); + return (((old ^ new) >> 32) & 1) ? old : new; +} +#endif + #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); @@ -331,6 +342,14 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .set_next_event_virt = erratum_set_next_event_tval_virt, }, #endif +#ifdef CONFIG_ARM64_ERRATUM_858921 + { + .match_type = ate_match_local_cap_id, + .id = (void *)ARM64_WORKAROUND_858921, + .desc = "ARM erratum 858921", + .read_cntvct_el0 = arm64_858921_read_cntvct_el0, + }, +#endif }; typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,