From patchwork Sun Apr 16 20:27:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 97467 Delivered-To: patch@linaro.org Received: by 10.140.109.52 with SMTP id k49csp1086856qgf; Sun, 16 Apr 2017 13:28:28 -0700 (PDT) X-Received: by 10.98.98.195 with SMTP id w186mr8299220pfb.10.1492374508147; Sun, 16 Apr 2017 13:28:28 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m188si8929486pfc.145.2017.04.16.13.28.27; Sun, 16 Apr 2017 13:28:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756925AbdDPU2Y (ORCPT + 15 others); Sun, 16 Apr 2017 16:28:24 -0400 Received: from mail-wr0-f179.google.com ([209.85.128.179]:33417 "EHLO mail-wr0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756858AbdDPU2T (ORCPT ); Sun, 16 Apr 2017 16:28:19 -0400 Received: by mail-wr0-f179.google.com with SMTP id l28so74358930wre.0 for ; Sun, 16 Apr 2017 13:28:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fBuEGvOhRtRexMlu0jKgvQaLg/kkA4BV9Lxxj7HKHtI=; b=UixGoZKgqfhGn1MrtWs+/eH8IlX76QinTdps/EtrF5tJsr+wElRNjafTLBdJYn68Mf Y2iYKwx6yB2LLhSDWwqAzWBWrZ2lrDXeIV9hZdONMHr72VFQn8JXpFnI6ztrW5/V4SUi Ybk4u2fo32yiZYZYp9ynI3FXp8FAM11AvsSYs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fBuEGvOhRtRexMlu0jKgvQaLg/kkA4BV9Lxxj7HKHtI=; b=JVl+OFHvOm5Z5+SnjTKJ0pWAFu/2t0tmh8SAhM9SeD/Jv1VfUoIIqYAQu+FXLyg/XZ oCvVvq8jfeg/SF95mKGGXI7cVqSQ3xT/938+CzssaDsmLmS0NxZXV6thrFuHzmh1orw+ D8QdkiPxXRVu7AC1uAcHeKng3ko8ig1qA2wrMekEMIvjKiGAxxrezvgGX+jqXQCkF5wh +NHkg5fuDICwrz5sUX0RUQFvMfmciY7gfsfNL0H94dwLBF+EbmnQXNTGR5fQJcBEyNAM I7HfCAYsnkxVgtGuimYbN8W7i1C7vDWTDWS0VNf4UEzhG+RVuAaxyM3sx2i6Mp6fiGqk Lhpw== X-Gm-Message-State: AN3rC/59LIjggWq0yOxf2FDcM6PaTV1CzcCBbEvSgaUhhJ+zNQpDZ1Ev 0NoIBlfYwZ4aNNUt X-Received: by 10.223.166.146 with SMTP id t18mr15346332wrc.15.1492374492847; Sun, 16 Apr 2017 13:28:12 -0700 (PDT) Received: from mai.lan ([2001:41d0:fe90:b800:20c0:6248:a385:db35]) by smtp.gmail.com with ESMTPSA id 81sm7732196wmj.9.2017.04.16.13.28.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 16 Apr 2017 13:28:12 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Marc Zyngier , Mark Rutland , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org (moderated list:ARM ARCHITECTED TIMER DRIVER) Subject: [PATCH 11/29] arm64: arch_timer: Make workaround methods optional Date: Sun, 16 Apr 2017 22:27:01 +0200 Message-Id: <1492374441-23336-11-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> References: <20170416202542.GV2078@mai> <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier Not all errata need to workaround all access types. Allow them to be optional. Acked-by: Thomas Gleixner Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/arch_timer.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index cc1e081..01917b4 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -60,8 +60,9 @@ extern const struct arch_timer_erratum_workaround *timer_unstable_counter_workar #define arch_timer_reg_read_stable(reg) \ ({ \ u64 _val; \ - if (needs_unstable_timer_counter_workaround()) \ - _val = timer_unstable_counter_workaround->read_##reg();\ + if (needs_unstable_timer_counter_workaround() && \ + timer_unstable_counter_workaround->read_##reg) \ + _val = timer_unstable_counter_workaround->read_##reg(); \ else \ _val = read_sysreg(reg); \ _val; \