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[209.132.180.67]) by mx.google.com with ESMTP id a96si1939554pli.151.2017.04.06.06.53.06; Thu, 06 Apr 2017 06:53:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934860AbdDFNwq (ORCPT + 14 others); Thu, 6 Apr 2017 09:52:46 -0400 Received: from mail-pg0-f45.google.com ([74.125.83.45]:35356 "EHLO mail-pg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934818AbdDFNwd (ORCPT ); Thu, 6 Apr 2017 09:52:33 -0400 Received: by mail-pg0-f45.google.com with SMTP id 81so37119467pgh.2 for ; Thu, 06 Apr 2017 06:52:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oNyvOih6c9AGh/s+I5OZj3Lb0Vucmuh8RcDftbFA2Bo=; b=I1PsNpMLvC1fTWKWh2fZ5ubqm7T9uuWyEmW1U5WgG/K9lMgYI4LBHhW3aC3QxOoX/X +rvXntutTXi5e/pgQpYB/1MV/uHrykNnaSKp2QH6gl0udZHct+NaWx8W7hgywk6ugwKl kfdUTy6sWCOr3NHC0+QtGDFBbn9HpZ3EXxX+I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oNyvOih6c9AGh/s+I5OZj3Lb0Vucmuh8RcDftbFA2Bo=; b=rQoM6VlxoPrBKxNKFnUuy7amegzw/rV84Nug0ThZOOSTLgEGjZvtgJcEDL2ijuslJp RGZf0i3kYeW5TaCNBXcQQGn/GOa2MQ8KcS7YXD7P021BWDgjPh1KYhCQUk1YMqE+PDBD JmUxAKiCVYR31OHc1s9WXygsZyFqRKM0MvvinxVABPvHW0P5Z8590j0Dkn+SiM0I2NMf t1V4PKDlJezF66AWd5b9kWHTbsxdXnvcptyXnMExaNktRUe9vkMQEAY/Y4WDCeNQur5x eN7NTtp50nnUGyrLZTFu9yDctXBualCvCgA9W6NxNLm4WUfnf9gEAcUOOXdCHbfGf/ZM Tj4g== X-Gm-Message-State: AFeK/H2azCALmKXKqtRWOCVkVBjfajbPsp9No8h10xKCBpxB35mhRzOImE2Wbq/c7T4QwLeA X-Received: by 10.84.232.79 with SMTP id f15mr43295574pln.90.1491486752243; Thu, 06 Apr 2017 06:52:32 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id v11sm4187210pfi.50.2017.04.06.06.52.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Apr 2017 06:52:31 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, james.hogan@imgtec.com, Matt Redfearn , Thomas Gleixner , Paul Burton , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Subject: [PATCH for-4.10 3/6] MIPS: Only change $28 to thread_info if coming from user mode Date: Thu, 6 Apr 2017 19:22:11 +0530 Message-Id: <1491486734-15668-4-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491486734-15668-1-git-send-email-amit.pundir@linaro.org> References: <1491486734-15668-1-git-send-email-amit.pundir@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Matt Redfearn The SAVE_SOME macro is used to save the execution context on all exceptions. If an exception occurs while executing user code, the stack is switched to the kernel's stack for the current task, and register $28 is switched to point to the current_thread_info, which is at the bottom of the stack region. If the exception occurs while executing kernel code, the stack is left, and this change ensures that register $28 is not updated. This is the correct behaviour when the kernel can be executing on the separate irq stack, because the thread_info will not be at the base of it. With this change, register $28 is only switched to it's kernel conventional usage of the currrent thread info pointer at the point at which execution enters kernel space. Doing it on every exception was redundant, but OK without an IRQ stack, but will be erroneous once that is introduced. Signed-off-by: Matt Redfearn Acked-by: Jason A. Donenfeld Cc: Thomas Gleixner Cc: James Hogan Cc: Paul Burton Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14742/ Signed-off-by: Ralf Baechle (cherry picked from commit 510d86362a27577f5ee23f46cfb354ad49731e61) Signed-off-by: Amit Pundir --- arch/mips/include/asm/stackframe.h | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.7.4 diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index eebf395..2f182bd 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -216,12 +216,19 @@ LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) + + /* Set thread_info if we're coming from user mode */ + mfc0 k0, CP0_STATUS + sll k0, 3 /* extract cu0 bit */ + bltz k0, 9f + ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON .set mips64 pref 0, 0($28) /* Prefetch the current pointer */ #endif +9: .set pop .endm