From patchwork Thu Mar 9 06:38:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95061 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp223624qgd; Wed, 8 Mar 2017 22:40:38 -0800 (PST) X-Received: by 10.98.43.204 with SMTP id r195mr12167094pfr.96.1489041638523; Wed, 08 Mar 2017 22:40:38 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n188si5495284pga.361.2017.03.08.22.40.38; Wed, 08 Mar 2017 22:40:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752692AbdCIGkg (ORCPT + 25 others); Thu, 9 Mar 2017 01:40:36 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:31342 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750770AbdCIGk0 (ORCPT ); Thu, 9 Mar 2017 01:40:26 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v296dFnE010809; Thu, 9 Mar 2017 00:39:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489041555; bh=626HsOfIsWNkiAD8Lm01u7cCnM2pFn+Ze76YUyHxO40=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vjylrQuoqH3wfMCtm408xMuwfiUs7SkOIr+6MZHBsGaZPAwOPmb3KU5z+bSAh316/ ZKrMTkyWTEfIK7KljKNiLC3A6bSlUXvDQmvNhEaV+tgQEl+79n5ia3EK2Vj3RQhzL1 IekZZZ7pDSgQ8eqNM7dY8hDT5ZoIGpo+FtyDFC2g= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v296dFkL007081; Thu, 9 Mar 2017 00:39:15 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Thu, 9 Mar 2017 00:39:15 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v296d9Oq009609; Thu, 9 Mar 2017 00:39:13 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , CC: , Subject: [RESEND PATCH v3 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup Date: Thu, 9 Mar 2017 12:08:59 +0530 Message-ID: <1489041545-15730-2-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1489041545-15730-1-git-send-email-kishon@ti.com> References: <1489041545-15730-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some platforms (like dra7xx) require only the least 28 bits of the corresponding 32 bit CPU address to be programmed in the address translation unit. This modified address is stored in io_base/mem_base/ cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for host mode where the address range is fixed, device mode requires different addresses to be programmed based on the host buffer address. Add a new ops to get the least 28 bits of the corresponding 32 bit CPU address and invoke it before programming the address translation unit. Acked-by: Joao Pinto Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pcie-designware.c | 3 +++ drivers/pci/dwc/pcie-designware.h | 1 + 2 files changed, 4 insertions(+) -- 1.7.9.5 diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 7e1fb7d..14ee7a3 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, { u32 retries, val; + if (pp->ops->cpu_addr_fixup) + cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr); + if (pci->iatu_unroll_enabled) { dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, lower_32_bits(cpu_addr)); diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index cd3b871..8f3dcb2 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -143,6 +143,7 @@ struct pcie_port { }; struct dw_pcie_ops { + u64 (*cpu_addr_fixup)(u64 cpu_addr); u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg); void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val); int (*link_up)(struct dw_pcie *pcie);