From patchwork Wed Feb 15 13:18:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 94007 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp2025630qgi; Wed, 15 Feb 2017 05:19:52 -0800 (PST) X-Received: by 10.84.254.66 with SMTP id a2mr36656370pln.57.1487164791991; Wed, 15 Feb 2017 05:19:51 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p17si3737201pge.220.2017.02.15.05.19.51; Wed, 15 Feb 2017 05:19:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751430AbdBONTk (ORCPT + 25 others); Wed, 15 Feb 2017 08:19:40 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:49530 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751375AbdBONTh (ORCPT ); Wed, 15 Feb 2017 08:19:37 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v1FDJ6eo026557; Wed, 15 Feb 2017 07:19:06 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v1FDJ6cv015280; Wed, 15 Feb 2017 07:19:06 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Wed, 15 Feb 2017 07:19:05 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v1FDIRHR019326; Wed, 15 Feb 2017 07:19:02 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jingoo Han , , , , , , , CC: , Kishon Vijay Abraham I Subject: [PATCH 07/10] PCI: dwc: designware: Fix style errors in pcie-designware.c Date: Wed, 15 Feb 2017 18:48:16 +0530 Message-ID: <1487164699-30708-8-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1487164699-30708-1-git-send-email-kishon@ti.com> References: <1487164699-30708-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Fix all checkpatch warnings and check errors in pcie-designware.c Acked-By: Joao Pinto Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pcie-designware.c | 42 ++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 21 deletions(-) -- 1.7.9.5 diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 237da48..622d416 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -40,13 +40,13 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val) return PCIBIOS_BAD_REGISTER_NUMBER; } - if (size == 4) + if (size == 4) { *val = readl(addr); - else if (size == 2) + } else if (size == 2) { *val = readw(addr); - else if (size == 1) + } else if (size == 1) { *val = readb(addr); - else { + } else { *val = 0; return PCIBIOS_BAD_REGISTER_NUMBER; } @@ -200,16 +200,15 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) for (i = 0; i < MAX_MSI_CTRLS; i++) { dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, - (u32 *)&val); + (u32 *)&val); if (val) { ret = IRQ_HANDLED; pos = 0; while ((pos = find_next_bit(&val, 32, pos)) != 32) { irq = irq_find_mapping(pp->irq_domain, - i * 32 + pos); - dw_pcie_wr_own_conf(pp, - PCIE_MSI_INTR0_STATUS + i * 12, - 4, 1 << pos); + i * 32 + pos); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + + i * 12, 4, 1 << pos); generic_handle_irq(irq); pos++; } @@ -275,8 +274,9 @@ static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) { int irq, pos0, i; - struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(desc); + struct pcie_port *pp; + pp = (struct pcie_port *)msi_desc_to_pci_sysdata(desc); pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, order_base_2(no_irqs)); if (pos0 < 0) @@ -338,7 +338,7 @@ static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos) } static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, - struct msi_desc *desc) + struct msi_desc *desc) { int irq, pos; struct pcie_port *pp = pdev->bus->sysdata; @@ -386,7 +386,7 @@ static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) { struct irq_data *data = irq_get_irq_data(irq); struct msi_desc *msi = irq_data_get_msi_desc(data); - struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi); + struct pcie_port *pp = (struct pcie_port *)msi_desc_to_pci_sysdata(msi); clear_irq_range(pp, irq, 1, data->hwirq); } @@ -428,7 +428,7 @@ int dw_pcie_link_up(struct dw_pcie *pci) } static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, - irq_hw_number_t hwirq) + irq_hw_number_t hwirq) { irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq); irq_set_chip_data(irq, domain->host_data); @@ -465,8 +465,8 @@ int dw_pcie_host_init(struct pcie_port *pp) cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); if (cfg_res) { - pp->cfg0_size = resource_size(cfg_res)/2; - pp->cfg1_size = resource_size(cfg_res)/2; + pp->cfg0_size = resource_size(cfg_res) / 2; + pp->cfg1_size = resource_size(cfg_res) / 2; pp->cfg0_base = cfg_res->start; pp->cfg1_base = cfg_res->start + pp->cfg0_size; } else if (!pp->va_cfg0_base) { @@ -505,8 +505,8 @@ int dw_pcie_host_init(struct pcie_port *pp) break; case 0: pp->cfg = win->res; - pp->cfg0_size = resource_size(pp->cfg)/2; - pp->cfg1_size = resource_size(pp->cfg)/2; + pp->cfg0_size = resource_size(pp->cfg) / 2; + pp->cfg1_size = resource_size(pp->cfg) / 2; pp->cfg0_base = pp->cfg->start; pp->cfg1_base = pp->cfg->start + pp->cfg0_size; break; @@ -612,7 +612,7 @@ int dw_pcie_host_init(struct pcie_port *pp) } static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val) + u32 devfn, int where, int size, u32 *val) { int ret, type; u32 busdev, cfg_size; @@ -651,7 +651,7 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, } static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, - u32 devfn, int where, int size, u32 val) + u32 devfn, int where, int size, u32 val) { int ret, type; u32 busdev, cfg_size; @@ -708,7 +708,7 @@ static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, } static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 *val) + int size, u32 *val) { struct pcie_port *pp = bus->sysdata; @@ -724,7 +724,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, } static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) + int where, int size, u32 val) { struct pcie_port *pp = bus->sysdata;