From patchwork Wed Feb 15 13:18:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 94008 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp2025652qgi; Wed, 15 Feb 2017 05:19:55 -0800 (PST) X-Received: by 10.98.94.2 with SMTP id s2mr37308532pfb.133.1487164795463; Wed, 15 Feb 2017 05:19:55 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p17si3737201pge.220.2017.02.15.05.19.55; Wed, 15 Feb 2017 05:19:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751467AbdBONTx (ORCPT + 25 others); Wed, 15 Feb 2017 08:19:53 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:35968 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751238AbdBONTu (ORCPT ); Wed, 15 Feb 2017 08:19:50 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v1FDJDmM029744; Wed, 15 Feb 2017 07:19:13 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v1FDJD6D015450; Wed, 15 Feb 2017 07:19:13 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Wed, 15 Feb 2017 07:19:12 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v1FDIRHT019326; Wed, 15 Feb 2017 07:19:09 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jingoo Han , , , , , , , CC: , Kishon Vijay Abraham I Subject: [PATCH 09/10] PCI: dwc: Create a new config symbol to enable pci dwc host Date: Wed, 15 Feb 2017 18:48:18 +0530 Message-ID: <1487164699-30708-10-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1487164699-30708-1-git-send-email-kishon@ti.com> References: <1487164699-30708-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that pci designware host has a separate file, create a new config symbol to select the host only driver. This will enable to independently select host support and endpoint suppor (when it's added). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/Kconfig | 26 +++++++++++++++----------- drivers/pci/dwc/Makefile | 3 ++- drivers/pci/dwc/pcie-designware.h | 29 +++++++++++++++++++++++++---- 3 files changed, 42 insertions(+), 16 deletions(-) -- 1.7.9.5 diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index deae261..ab92a0c 100644 --- a/drivers/pci/dwc/Kconfig +++ b/drivers/pci/dwc/Kconfig @@ -3,13 +3,17 @@ menu "DesignWare PCI Core Support" config PCIE_DW bool + +config PCIE_DW_HOST + bool depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW config PCI_DRA7XX bool "TI DRA7xx PCIe controller" depends on OF && HAS_IOMEM && TI_PIPE3 depends on PCI_MSI_IRQ_DOMAIN - select PCIE_DW + select PCIE_DW_HOST help Enables support for the PCIe controller in the DRA7xx SoC. There are two instances of PCIe controller in DRA7xx. This controller can @@ -18,7 +22,7 @@ config PCI_DRA7XX config PCIE_DW_PLAT bool "Platform bus based DesignWare PCIe Controller" depends on PCI_MSI_IRQ_DOMAIN - select PCIE_DW + select PCIE_DW_HOST ---help--- This selects the DesignWare PCIe controller support. Select this if you have a PCIe controller on Platform bus. @@ -32,21 +36,21 @@ config PCI_EXYNOS depends on SOC_EXYNOS5440 depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS - select PCIE_DW + select PCIE_DW_HOST config PCI_IMX6 bool "Freescale i.MX6 PCIe controller" depends on SOC_IMX6Q depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS - select PCIE_DW + select PCIE_DW_HOST config PCIE_SPEAR13XX bool "STMicroelectronics SPEAr PCIe controller" depends on ARCH_SPEAR13XX depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS - select PCIE_DW + select PCIE_DW_HOST help Say Y here if you want PCIe support on SPEAr13XX SoCs. @@ -55,7 +59,7 @@ config PCI_KEYSTONE depends on ARCH_KEYSTONE depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS - select PCIE_DW + select PCIE_DW_HOST help Say Y here if you want to enable PCI controller support on Keystone SoCs. The PCI controller on Keystone is based on Designware hardware @@ -67,7 +71,7 @@ config PCI_LAYERSCAPE depends on OF && (ARM || ARCH_LAYERSCAPE) depends on PCI_MSI_IRQ_DOMAIN select MFD_SYSCON - select PCIE_DW + select PCIE_DW_HOST help Say Y here if you want PCIe controller support on Layerscape SoCs. @@ -76,7 +80,7 @@ config PCI_HISI bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers" depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS - select PCIE_DW + select PCIE_DW_HOST help Say Y here if you want PCIe controller support on HiSilicon Hip05 and Hip06 SoCs @@ -86,7 +90,7 @@ config PCIE_QCOM depends on ARCH_QCOM && OF depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS - select PCIE_DW + select PCIE_DW_HOST help Say Y here to enable PCIe controller support on Qualcomm SoCs. The PCIe controller uses the Designware core plus Qualcomm-specific @@ -97,7 +101,7 @@ config PCIE_ARMADA_8K depends on ARCH_MVEBU depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS - select PCIE_DW + select PCIE_DW_HOST help Say Y here if you want to enable PCIe controller support on Armada-8K SoCs. The PCIe controller on Armada-8K is based on @@ -109,7 +113,7 @@ config PCIE_ARTPEC6 depends on MACH_ARTPEC6 depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS - select PCIE_DW + select PCIE_DW_HOST help Say Y here to enable PCIe controller support on Axis ARTPEC-6 SoCs. This PCIe controller uses the DesignWare core. diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile index 3b57e55..a2df13c 100644 --- a/drivers/pci/dwc/Makefile +++ b/drivers/pci/dwc/Makefile @@ -1,4 +1,5 @@ -obj-$(CONFIG_PCIE_DW) += pcie-designware.o pcie-designware-host.o +obj-$(CONFIG_PCIE_DW) += pcie-designware.o +obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index 3054770..cd3b871 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -161,10 +161,6 @@ struct dw_pcie { int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); -irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); -void dw_pcie_msi_init(struct pcie_port *pp); -void dw_pcie_setup_rc(struct pcie_port *pp); -int dw_pcie_host_init(struct pcie_port *pp); u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg); void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val); @@ -174,4 +170,29 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, u64 cpu_addr, u64 pci_addr, u32 size); void dw_pcie_setup(struct dw_pcie *pci); + +#ifdef CONFIG_PCIE_DW_HOST +irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); +void dw_pcie_msi_init(struct pcie_port *pp); +void dw_pcie_setup_rc(struct pcie_port *pp); +int dw_pcie_host_init(struct pcie_port *pp); +#else +static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) +{ + return IRQ_NONE; +} + +static inline void dw_pcie_msi_init(struct pcie_port *pp) +{ +} + +static inline void dw_pcie_setup_rc(struct pcie_port *pp) +{ +} + +static inline int dw_pcie_host_init(struct pcie_port *pp) +{ + return 0; +} +#endif #endif /* _PCIE_DESIGNWARE_H */