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[209.132.180.67]) by mx.google.com with ESMTP id g28si8354989pfd.227.2017.02.08.15.24.35; Wed, 08 Feb 2017 15:24:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751716AbdBHXY2 (ORCPT + 25 others); Wed, 8 Feb 2017 18:24:28 -0500 Received: from mail-wm0-f46.google.com ([74.125.82.46]:38134 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750940AbdBHXY1 (ORCPT ); Wed, 8 Feb 2017 18:24:27 -0500 Received: by mail-wm0-f46.google.com with SMTP id r141so3398535wmg.1 for ; Wed, 08 Feb 2017 15:22:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BQgmboPzroU++X9fExkkH5mvXQiU6hBBpPdYVKuLM5g=; b=RZ+StSuVOhpr5qFYpygLdYSsNaD7V+iEbQoZmJOKY6ZyrQ4q/kfL9i8feU905j7wpZ O2mAMCb4IJ7RrkvacaAgn3R6ilrztoWmf9hVM2uyybfEAbnC4jhfbINruxUrB04b42fE BQHNClMQlVwgMV1gsgYB7LX7vsU7WAyVXZwtM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BQgmboPzroU++X9fExkkH5mvXQiU6hBBpPdYVKuLM5g=; b=CmjARjcoBUi+FHipLXXwOp642K/o/P7CCGTG3KBZDTuWMCC8FnS68hUt0dYTFI2NGJ hrn624s7b0nPK6KBGp4CYzH6syKlexqijkx0yzLnPeE7Mj7+d5NKReZKHpf9cCmgQUVq NhriB3BIlSMGysyMWUdHZYfndW7OQD75w6CztYM/6MkxO2xTwjS5SE1LBGPydnXw8WKY N89ihusX3Z6EMBg8GFkdTCaSoPXBTaJr+34GMKrdRb6ffVKb889zLnabGqz3nZYhkmy3 nN+ZKcd1zz69Z6hhpdYvyWZRd2gj4HeMNHzttzqrAFex9aQAuRwEh/f1k0FELB/qNsWh lodg== X-Gm-Message-State: AMke39kgyteMoAcX5PtNqCkL9AezqhZOytcfkmpCOlRB3aieM5F+4n92vDmu5JxvwWk+WpKM X-Received: by 10.28.148.76 with SMTP id w73mr20125738wmd.74.1486595774116; Wed, 08 Feb 2017 15:16:14 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:3f16:bcf7:601c:a13b]) by smtp.gmail.com with ESMTPSA id u42sm15422821wrc.1.2017.02.08.15.16.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Feb 2017 15:16:13 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: Ding Tianhong , Mark Rutland , Marc Zyngier , linux-kernel@vger.kernel.org (open list:CLOCKSOURCE, CLOCKEVENT DRIVERS), linux-arm-kernel@lists.infradead.org (moderated list:ARM ARCHITECTED TIMER DRIVER) Subject: [PATCH 10/10] clocksource/drivers/arm_arch_timer: Work around Hisilicon erratum 161010101 Date: Thu, 9 Feb 2017 00:14:44 +0100 Message-Id: <1486595685-10232-10-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486595685-10232-1-git-send-email-daniel.lezcano@linaro.org> References: <20170208231208.GB12695@mai> <1486595685-10232-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ding Tianhong Erratum Hisilicon-161010101 says that the ARM generic timer counter "has the potential to contain an erroneous value when the timer value changes". Accesses to TVAL (both read and write) are also affected due to the implicit counter read. Accesses to CVAL are not affected. The workaround is to reread the system count registers until the value of the second read is larger than the first one by less than 32, the system counter can be guaranteed not to return wrong value twice by back-to-back read and the error value is always larger than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL. Signed-off-by: Ding Tianhong [Mark: split patch, fix Kconfig, reword commit message] Signed-off-by: Mark Rutland Acked-by: Daniel Lezcano Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 10 ++++++++ drivers/clocksource/arm_arch_timer.c | 49 ++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 1945af2..3356ab8 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -356,6 +356,16 @@ config FSL_ERRATUM_A008585 value"). The workaround will only be active if the fsl,erratum-a008585 property is found in the timer node. +config HISILICON_ERRATUM_161010101 + bool "Workaround for Hisilicon Erratum 161010101" + default y + select ARM_ARCH_TIMER_OOL_WORKAROUND + depends on ARM_ARCH_TIMER && ARM64 + help + This option enables a workaround for Hisilicon Erratum + 161010101. The workaround will be active if the hisilicon,erratum-161010101 + property is found in the timer node. + config ARM_GLOBAL_TIMER bool "Support for the ARM global timer" if COMPILE_TEST select CLKSRC_OF if OF diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 2af0739..7b06aef 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -130,6 +130,47 @@ static u64 notrace fsl_a008585_read_cntvct_el0(void) } #endif +#ifdef CONFIG_HISILICON_ERRATUM_161010101 +/* + * Verify whether the value of the second read is larger than the first by + * less than 32 is the only way to confirm the value is correct, so clear the + * lower 5 bits to check whether the difference is greater than 32 or not. + * Theoretically the erratum should not occur more than twice in succession + * when reading the system counter, but it is possible that some interrupts + * may lead to more than twice read errors, triggering the warning, so setting + * the number of retries far beyond the number of iterations the loop has been + * observed to take. + */ +#define __hisi_161010101_read_reg(reg) ({ \ + u64 _old, _new; \ + int _retries = 50; \ + \ + do { \ + _old = read_sysreg(reg); \ + _new = read_sysreg(reg); \ + _retries--; \ + } while (unlikely((_new - _old) >> 5) && _retries); \ + \ + WARN_ON_ONCE(!_retries); \ + _new; \ +}) + +static u32 notrace hisi_161010101_read_cntp_tval_el0(void) +{ + return __hisi_161010101_read_reg(cntp_tval_el0); +} + +static u32 notrace hisi_161010101_read_cntv_tval_el0(void) +{ + return __hisi_161010101_read_reg(cntv_tval_el0); +} + +static u64 notrace hisi_161010101_read_cntvct_el0(void) +{ + return __hisi_161010101_read_reg(cntvct_el0); +} +#endif + #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL; EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); @@ -146,6 +187,14 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, }, #endif +#ifdef CONFIG_HISILICON_ERRATUM_161010101 + { + .id = "hisilicon,erratum-161010101", + .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, + .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, + .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, + }, +#endif }; #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */